Commit 99f03d5b authored by GuillemCabo's avatar GuillemCabo
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add overflow spec

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\section{General purpose of the module}
This module shall detect if an overflow of a given counter is about to happen, if any counter reaches the maximum value an interrupt shall be risen by the overflow module. Only one interrupt is required, the counter causing the interrupt shall be identified by a signal called overflow interrupt vector (over\_intr\_vect\_o) that will encode in one-hot fashion the offending counter or counters.\\
\\
Overflow detection shall be optional for each individual counter, hardware for overflow detection shall be present for all the counters but software shall be able to control through an overflow interrupt mask (over\_intr\_mask\_i) what counters can actually generate an interrupt.\\
\\
A dedicated enable signal shall be provided. Enable is active high.\\
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Interrupt can not be active if the unit is disabled. The unit is considered enabled if the unit is not in hard or soft reset and the enable is high.\\
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The whole unit shall use combinational logic, inputs and outputs are registered externally at the rising edge of the clock. The required inputs and outputs will be wires, names, types and default sizes are provided in section \ref{interface}.\\
\\
\section{Design placement}
\label{chapter2}
This modules is meant to be instantiated by the interface agnostic PMU (PMU\_raw.sv). Only one instance of this module is required.
%This module is meant to be a blackbox inside the chisel code. It belongs to the Drac class in the \emph{rocket.scala} file. We can have as many instances of this module as cores are instantiated in the SoC. Currently only single core operation has been tested.
\section{Parameters}
\label{chapter3}
This module requires two integer parameters.REG\_WIDTH and N\_COUNTERS. \\
\textbf{REG\_WIDTH} defines the number of bits that a counter has.\\
\textbf{N\_COUNTERS} defines the amount of counters that are available in the PMU.\\
Given the previous parameters the unit shall generate correct RTL without any manual modification to the source code.
%The instance of this module takes no parameters, signal widths are hard-coded to match the SoC.
%Internal parameters and structures such as signals for requests and responses of the caches are imported from drac\_pkg.
\ No newline at end of file
\section{Interface}\label{interface}
\label{chapter 4}
Interface signals of the module are listed in the table below.
%TODO
%\begin{table}[H]
% \centering
% \begin{tabular}{lllll}
% \hline
% Port\_Name & Direction & Width & Index & Description \\
% \hline
% CLK & INPUT & 1 & - & Main clock, up to 200MHz \\
% RST & INPUT & 1 & - & Hard reset. Active LOW \\
% SOFT\_RST & INPUT & 1 & - & Soft reset. Active LOW \\
% RESET\_ADDRESS & INPUT & 40 & - & Inital address of PC after soft or hard reset \\
% CSR\_RW\_RDATA & INPUT & 64 & - & - \\
% \end{tabular}
%\end{table}
\section{Reset behavior}
The module contains two reset signals. One synchronous active high reset enabled by software called softrst\_i, the other is the global reset, it is asynchronous and active low.\\
\\
Any reset when active shall clear any internal register and set them to 0. Interruptions shall become inactive while the unit is in reset.
\section{What could not happen}
All signals except registers used to track previous state of the interrupts shall not be registered.\\
\\
Interruptions shall be low while the unit is in reset.\\
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Overflow interruption vector shall not decrease in value unless the unit is reset or soft-reset.\\
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The overflow interruption shall not decrease unless the unit is reset or soft-reset.
\ No newline at end of file
\section{Behavior}
The module identifies the overflow of a counter by performing an and reduction of the incoming counter signals. Detected overflowing counters will only be signaled to the output after applying a bit by bit and operation between the detected overflow signal and the current overflow mask.\\
\\
The unit is considered disabled when rstn\_i is 0 or softrst\_i is 1 or en\_i is 0.\\
\\
The previous state of the interrupt vector is stored to prevent missing the interrupt once the counter overflows. The output interrupt is te result of an or reduction of the masked overflow signals (masked\_overflow) and the past interruption vector (past\_intr\_vect) if the unit is enabled, otherwise the output is 0. In other words, if any bit in the past interruption vector or masked overflow signals the interuption while the unit is active the interrupt is active.\\
\\
\subsection{Packages and structures}
No packages and structures are used in this module.
\section{Special cases, corner cases}
If the unit is disabled instead but soft reset is never activated the previous state of the interrupt vector will not be cleared and therefore the interrupt will trigger again as soon as the unit is enabled. Since the internal state is not visible for software developers if not used correctly it may lead to unexpected behavior.
CC=pdflatex
all: spec
spec: main.tex 1-Section.tex 2-Section.tex 3-Section.tex 4-Section.tex 5-Section.tex 6-Section.tex 7-Section.tex 8-Section.tex
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\huge PMU\_overflow specification version v1 \\ % The assignment title
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\author{ Guillem Cabo Pitarch} % Your name
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