Commit 86907eee authored by GuillemCabo's avatar GuillemCabo
Browse files

fix width mismatch

parent 7e6c0003
...@@ -588,7 +588,7 @@ end ...@@ -588,7 +588,7 @@ end
//data phase - slave response //data phase - slave response
assign slv_index = address_phase.master_addr_Q[$clog2(N_REGS)+1:2]; assign slv_index = address_phase.master_addr_Q[$clog2(N_REGS)+1:2];
assign invalid_index = address_phase.master_addr_Q[$clog2(N_REGS)+1:2] >= N_REGS? 1'b1:1'b0; assign invalid_index = int'(address_phase.master_addr_Q[$clog2(N_REGS)+1:2]) >= N_REGS? 1'b1:1'b0;
assign hrdata_o = dread_slave; assign hrdata_o = dread_slave;
assign hreadyo_o = complete_transfer_status [0]; assign hreadyo_o = complete_transfer_status [0];
......
...@@ -119,7 +119,7 @@ module PMU_quota # ...@@ -119,7 +119,7 @@ module PMU_quota #
//prevent overflow of statemachine //prevent overflow of statemachine
state_int <= 0; state_int <= 0;
end else begin end else begin
state_int <= N_BITS_STATES'(state_int + 1); state_int <= N_BITS_STATES'(state_int + 1'b1);
end end
end end
end end
......
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