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CAOS_HW
HDL_IP
SafeSU
Commits
86443a68
Commit
86443a68
authored
Jul 29, 2020
by
Guillem
Browse files
set 24 counter; Change RDC events
parent
e7e1c09f
Changes
2
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Inline
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hdl/PMU_raw.sv
View file @
86443a68
...
...
@@ -389,13 +389,13 @@ end
//be hardcoded to specific corssbars outputs
wire
[
MCCU_N_EVENTS
-
1
:
0
]
MCCU_events_int
[
0
:
MCCU_N_CORES
-
1
];
//core_0
assign
MCCU_events_int
[
0
]
=
{{
events_int
[
1
]
}
,
{
events_int
[
0
]
}}
;
assign
MCCU_events_int
[
0
]
=
{{
events_int
[
5
]
}
,
{
events_int
[
12
]
}}
;
//core_1
assign
MCCU_events_int
[
1
]
=
{{
events_int
[
3
]
}
,
{
events_int
[
2
]
}}
;
assign
MCCU_events_int
[
1
]
=
{{
events_int
[
6
]
}
,
{
events_int
[
9
]
}}
;
//core_2
assign
MCCU_events_int
[
2
]
=
{{
events_int
[
5
]
}
,
{
events_int
[
4
]
}}
;
assign
MCCU_events_int
[
2
]
=
{{
events_int
[
7
]
}
,
{
events_int
[
10
]
}}
;
//core_3
assign
MCCU_events_int
[
3
]
=
{{
events_int
[
7
]
}
,
{
events_int
[
6
]
}}
;
assign
MCCU_events_int
[
3
]
=
{{
events_int
[
8
]
}
,
{
events_int
[
11
]
}}
;
//NON-PARAMETRIC This can be autogenenerated TODO
wire
[
MCCU_WEIGHTS_WIDTH
-
1
:
0
]
MCCU_events_weights_int
[
0
:
MCCU_N_CORES
-
1
]
...
...
hdl/pmu_ahb.sv
View file @
86443a68
...
...
@@ -35,15 +35,12 @@
// -- PMU specific parameters
// Cores connected to MCCU
localparam
MCCU_N_CORES
=
4
,
// Total amount of registers
parameter
integer
N_REGS
=
28
,
// Total amount of registers
parameter
integer
N_REGS
=
43
,
// Number of configuration registers
localparam
PMU_CFG
=
1
,
// Number of counters
localparam
PMU_COUNTERS
=
9
,
//TODO: for now it is hardcoded but this may be calculated given the
//features, n_cores and N_events in the future
localparam
PMU_TOTAL_REGS
=
N_REGS
localparam
PMU_COUNTERS
=
24
)
(
input
wire
rstn_i
,
...
...
@@ -320,7 +317,6 @@ end
//----------------------------------------------
//------------- PMU_raw instance
//----------------------------------------------
//assert(PMU_TOTAL_REGS == N_REGS);
wire
[
REG_WIDTH
-
1
:
0
]
pmu_regs_int
[
0
:
N_REGS
-
1
];
wire
ahb_write_req
;
assign
ahb_write_req
=
address_phase
.
write
&&
address_phase
.
select
;
...
...
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