Commit 7ff5353e authored by GuillemCabo's avatar GuillemCabo
Browse files

add Port table

parent 30a05809
\section{Interface}\label{interface}
\label{chapter 4}
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llllll}
\hline
Port Name & Direction & Width & Index & Comment & Comment Source
\\
\hline
clk\_i & INPUT & 1 & - & Width of data registers & module port
\\
rstn\_i & INPUT & 1 & - & Active low asyncronous reset. It... & module port
\\
enable\_i & INPUT & 1 & - & can be generated & module port
\\
events\_i & INPUT & 8 & [0:1][3:0] & Monitored events that can genera... & module port
\\
quota\_i & INPUT & 64 & [0:1][31:0] & Quota for each of the cores, int... & module port
\\
update\_quota\_i & INPUT & 2 & [0:1] & Update quota. Set quota\_int to t... & module port
\\
quota\_o & OUTPUT & 64 & [0:1][31:0] & Internal quota available & module port
\\
events\_weights\_i & INPUT & 64 & [0:1][0:3][7:0] & internally registered, set by so... & module port
\\
\hline
\end{tabular}
\caption{Ports of module MCCU}
\label{port:MCCU}
\end{table}
Interface signals of the module are listed in the table below.
Interface signals of the module are listed in table \ref{port:MCCU}
%TODO
%\begin{table}[H]
......
\section{Interface}\label{interface}
\label{chapter 4}
Interface signals of the module are listed in the table below.
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llllll}
\hline
Port Name & Direction & Width & Index & Comment & Comment Source
\\
\hline
clk\_i & INPUT & 1 & - & Global Clock Signal & module port
\\
rstn\_i & INPUT & 1 & - & Global Reset Signal. This Signal... & module port
\\
softrst\_i & INPUT & 1 & - & Active HIGH & module port
\\
en\_i & INPUT & 1 & - & Active HIGH & module port
\\
we\_i & INPUT & 1 & - & TODO: Consider if is worth addin... & module port
\\
regs\_i & INPUT & 288 & [0:8][31:0] & registers & module port
\\
regs\_o & OUTPUT & 288 & [0:8][31:0] & - & -\\
events\_i & INPUT & 9 & [8:0] & external signals from Soc events & module port
\\
\hline
\end{tabular}
\caption{Ports of module PMU\_counters}
\label{port:PMU_counters}
\end{table}
Interface signals of the module are listed in table \ref{port:PMU_counters}
%TODO
%\begin{table}[H]
......
\section{Interface}\label{interface}
\label{chapter 4}
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llllll}
\hline
Port Name & Direction & Width & Index & Comment & Comment Source
\\
\hline
clk\_i & INPUT & 1 & - & Global Clock Signal & module port
\\
rstn\_i & INPUT & 1 & - & Global Reset Signal. This Signal... & module port
\\
softrst\_i & INPUT & 1 & - & Active HIGH & module port
\\
en\_i & INPUT & 1 & - & Active HIGH & module port
\\
counter\_regs\_i & INPUT & 288 & [0:8][31:0] & Input wire from wrapper containi... & module port
\\
over\_intr\_mask\_i & INPUT & 9 & [8:0] & updated either & module port
\\
intr\_overflow\_o & OUTPUT & 1 & - & Global interrupt overflow & module port
\\
over\_intr\_vect\_o & OUTPUT & 9 & [8:0] & Output of the Overflow interrupt... & module port
\\
\hline
\end{tabular}
\caption{Ports of module PMU\_overflow}
\label{port:PMU_overflow}
\end{table}
Interface signals of the module are listed in the table below.
Interface signals of the module are listed in table \ref{port:PMU_overflow}
%TODO
%\begin{table}[H]
......
\section{Interface}\label{interface}
\label{chapter 4}
Interface signals of the module are listed in the table below.
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llllll}
\hline
Port Name & Direction & Width & Index & Comment & Comment Source
\\
\hline
clk\_i & INPUT & 1 & - & Global Clock Signal & module port
\\
rstn\_i & INPUT & 1 & - & Global Reset Signal. This Signal... & module port
\\
counter\_value\_i & INPUT & 288 & [0:8][31:0] & Input wire from wrapper containi... & module port
\\
softrst\_i & INPUT & 1 & - & Active HIGH & module port
\\
quota\_limit\_i & INPUT & 32 & [31:0] & sum\_all\_counters (counter\_value\_... & module port
\\
quota\_mask\_i & INPUT & 9 & [8:0] & total quota that triggers the in... & module port
\\
intr\_quota\_o & OUTPUT & 1 & - & Interrupt quota & module port
\\
\hline
\end{tabular}
\caption{Ports of module PMU\_quota}
\label{port:PMU_quota}
\end{table}
Interface signals of the module are listed in table \ref{port:PMU_quota}
%TODO
%\begin{table}[H]
......
\section{Interface}\label{interface}
\label{chapter 4}
Interface signals of the module are listed in the table below.
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llllll}
\hline
Port Name & Direction & Width & Index & Comment & Comment Source
\\
\hline
clk\_i & INPUT & 1 & - & Width of data registers & module port
\\
rstn\_i & INPUT & 1 & - & Active low asyncronous reset. It... & module port
\\
enable\_i & INPUT & 1 & - & can be generated & module port
\\
events\_i & INPUT & 8 & [0:3][1:0] & Monitored events that can genera... & module port
\\
events\_weights\_i & INPUT & 64 & [0:3][0:1][7:0] & internally registered, set by so... & module port
\\
interruption\_rdc\_o & OUTPUT & 1 & - & Event longer than specified weig... & module port
\\
interruption\_vector\_rdc\_o & OUTPUT & 8 & [0:3][1:0] & Interruption vector to indicate ... & module port
\\
watermark\_o & OUTPUT & 64 & [0:3][0:1][7:0] & High watermark for each event of... & module port
\\
\hline
\end{tabular}
\caption{Ports of module RDC}
\label{port:RDC}
\end{table}
Interface signals of the module are listed in table \ref{port:RDC}
%TODO
%\begin{table}[H]
......
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