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CAOS_HW
HDL_IP
SafeSU
Commits
7ff5353e
Commit
7ff5353e
authored
Sep 22, 2020
by
GuillemCabo
Browse files
add Port table
parent
30a05809
Changes
5
Hide whitespace changes
Inline
Side-by-side
docs/MCCU_specification/4-Section.tex
View file @
7ff5353e
\section
{
Interface
}
\label
{
interface
}
\label
{
chapter 4
}
\begin{table}
[ht]
\scriptsize
\centering
\begin{tabular}
{
llllll
}
\hline
Port Name
&
Direction
&
Width
&
Index
&
Comment
&
Comment Source
\\
\hline
clk
\_
i
&
INPUT
&
1
&
-
&
Width of data registers
&
module port
\\
rstn
\_
i
&
INPUT
&
1
&
-
&
Active low asyncronous reset. It...
&
module port
\\
enable
\_
i
&
INPUT
&
1
&
-
&
can be generated
&
module port
\\
events
\_
i
&
INPUT
&
8
&
[0:1][3:0]
&
Monitored events that can genera...
&
module port
\\
quota
\_
i
&
INPUT
&
64
&
[0:1][31:0]
&
Quota for each of the cores, int...
&
module port
\\
update
\_
quota
\_
i
&
INPUT
&
2
&
[0:1]
&
Update quota. Set quota
\_
int to t...
&
module port
\\
quota
\_
o
&
OUTPUT
&
64
&
[0:1][31:0]
&
Internal quota available
&
module port
\\
events
\_
weights
\_
i
&
INPUT
&
64
&
[0:1][0:3][7:0]
&
internally registered, set by so...
&
module port
\\
\hline
\end{tabular}
\caption
{
Ports of module MCCU
}
\label
{
port:MCCU
}
\end{table}
Interface signals of the module are listed in
the
table
below.
Interface signals of the module are listed in table
\ref
{
port:MCCU
}
%TODO
%\begin{table}[H]
...
...
docs/PMU_counters_specification/4-Section.tex
View file @
7ff5353e
\section
{
Interface
}
\label
{
interface
}
\label
{
chapter 4
}
Interface signals of the module are listed in the table below.
\begin{table}
[ht]
\scriptsize
\centering
\begin{tabular}
{
llllll
}
\hline
Port Name
&
Direction
&
Width
&
Index
&
Comment
&
Comment Source
\\
\hline
clk
\_
i
&
INPUT
&
1
&
-
&
Global Clock Signal
&
module port
\\
rstn
\_
i
&
INPUT
&
1
&
-
&
Global Reset Signal. This Signal...
&
module port
\\
softrst
\_
i
&
INPUT
&
1
&
-
&
Active HIGH
&
module port
\\
en
\_
i
&
INPUT
&
1
&
-
&
Active HIGH
&
module port
\\
we
\_
i
&
INPUT
&
1
&
-
&
TODO: Consider if is worth addin...
&
module port
\\
regs
\_
i
&
INPUT
&
288
&
[0:8][31:0]
&
registers
&
module port
\\
regs
\_
o
&
OUTPUT
&
288
&
[0:8][31:0]
&
-
&
-
\\
events
\_
i
&
INPUT
&
9
&
[8:0]
&
external signals from Soc events
&
module port
\\
\hline
\end{tabular}
\caption
{
Ports of module PMU
\_
counters
}
\label
{
port:PMU
_
counters
}
\end{table}
Interface signals of the module are listed in table
\ref
{
port:PMU
_
counters
}
%TODO
%\begin{table}[H]
...
...
docs/PMU_overflow_specification/4-Section.tex
View file @
7ff5353e
\section
{
Interface
}
\label
{
interface
}
\label
{
chapter 4
}
\begin{table}
[ht]
\scriptsize
\centering
\begin{tabular}
{
llllll
}
\hline
Port Name
&
Direction
&
Width
&
Index
&
Comment
&
Comment Source
\\
\hline
clk
\_
i
&
INPUT
&
1
&
-
&
Global Clock Signal
&
module port
\\
rstn
\_
i
&
INPUT
&
1
&
-
&
Global Reset Signal. This Signal...
&
module port
\\
softrst
\_
i
&
INPUT
&
1
&
-
&
Active HIGH
&
module port
\\
en
\_
i
&
INPUT
&
1
&
-
&
Active HIGH
&
module port
\\
counter
\_
regs
\_
i
&
INPUT
&
288
&
[0:8][31:0]
&
Input wire from wrapper containi...
&
module port
\\
over
\_
intr
\_
mask
\_
i
&
INPUT
&
9
&
[8:0]
&
updated either
&
module port
\\
intr
\_
overflow
\_
o
&
OUTPUT
&
1
&
-
&
Global interrupt overflow
&
module port
\\
over
\_
intr
\_
vect
\_
o
&
OUTPUT
&
9
&
[8:0]
&
Output of the Overflow interrupt...
&
module port
\\
\hline
\end{tabular}
\caption
{
Ports of module PMU
\_
overflow
}
\label
{
port:PMU
_
overflow
}
\end{table}
Interface signals of the module are listed in
the
table
be
low
.
Interface signals of the module are listed in table
\ref
{
port:PMU
_
overf
low
}
%TODO
%\begin{table}[H]
...
...
docs/PMU_quota_specification/4-Section.tex
View file @
7ff5353e
\section
{
Interface
}
\label
{
interface
}
\label
{
chapter 4
}
Interface signals of the module are listed in the table below.
\begin{table}
[ht]
\scriptsize
\centering
\begin{tabular}
{
llllll
}
\hline
Port Name
&
Direction
&
Width
&
Index
&
Comment
&
Comment Source
\\
\hline
clk
\_
i
&
INPUT
&
1
&
-
&
Global Clock Signal
&
module port
\\
rstn
\_
i
&
INPUT
&
1
&
-
&
Global Reset Signal. This Signal...
&
module port
\\
counter
\_
value
\_
i
&
INPUT
&
288
&
[0:8][31:0]
&
Input wire from wrapper containi...
&
module port
\\
softrst
\_
i
&
INPUT
&
1
&
-
&
Active HIGH
&
module port
\\
quota
\_
limit
\_
i
&
INPUT
&
32
&
[31:0]
&
sum
\_
all
\_
counters (counter
\_
value
\_
...
&
module port
\\
quota
\_
mask
\_
i
&
INPUT
&
9
&
[8:0]
&
total quota that triggers the in...
&
module port
\\
intr
\_
quota
\_
o
&
OUTPUT
&
1
&
-
&
Interrupt quota
&
module port
\\
\hline
\end{tabular}
\caption
{
Ports of module PMU
\_
quota
}
\label
{
port:PMU
_
quota
}
\end{table}
Interface signals of the module are listed in table
\ref
{
port:PMU
_
quota
}
%TODO
%\begin{table}[H]
...
...
docs/RDC_specification/4-Section.tex
View file @
7ff5353e
\section
{
Interface
}
\label
{
interface
}
\label
{
chapter 4
}
Interface signals of the module are listed in the table below.
\begin{table}
[ht]
\scriptsize
\centering
\begin{tabular}
{
llllll
}
\hline
Port Name
&
Direction
&
Width
&
Index
&
Comment
&
Comment Source
\\
\hline
clk
\_
i
&
INPUT
&
1
&
-
&
Width of data registers
&
module port
\\
rstn
\_
i
&
INPUT
&
1
&
-
&
Active low asyncronous reset. It...
&
module port
\\
enable
\_
i
&
INPUT
&
1
&
-
&
can be generated
&
module port
\\
events
\_
i
&
INPUT
&
8
&
[0:3][1:0]
&
Monitored events that can genera...
&
module port
\\
events
\_
weights
\_
i
&
INPUT
&
64
&
[0:3][0:1][7:0]
&
internally registered, set by so...
&
module port
\\
interruption
\_
rdc
\_
o
&
OUTPUT
&
1
&
-
&
Event longer than specified weig...
&
module port
\\
interruption
\_
vector
\_
rdc
\_
o
&
OUTPUT
&
8
&
[0:3][1:0]
&
Interruption vector to indicate ...
&
module port
\\
watermark
\_
o
&
OUTPUT
&
64
&
[0:3][0:1][7:0]
&
High watermark for each event of...
&
module port
\\
\hline
\end{tabular}
\caption
{
Ports of module RDC
}
\label
{
port:RDC
}
\end{table}
Interface signals of the module are listed in table
\ref
{
port:RDC
}
%TODO
%\begin{table}[H]
...
...
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