Commit 7e6c0003 authored by Guillem Cabo's avatar Guillem Cabo
Browse files

Merge branch 'jk/FT-rebase' into 'develop'

add fault tolerance

See merge request !11
parents a383924a 9d9db298
pmu_ahb/
AXI_PMU_interface_v1_0_S00_AXI/
AXI_PMU/
dummy_ahb/
PMU_raw/
......@@ -244,7 +244,7 @@
// S_AXI_AWVALID_i and S_AXI_WVALID_i are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -278,7 +278,7 @@
// This process is used to latch the address when both
// S_AXI_AWVALID_i and S_AXI_WVALID_i are valid.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -299,7 +299,7 @@
// S_AXI_AWVALID_i and S_AXI_WVALID_i are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -331,7 +331,7 @@
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID_i && axi_awready && S_AXI_AWVALID_i;
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin : reset_all
......@@ -434,7 +434,7 @@
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -468,7 +468,7 @@
// The read address is also latched when S_AXI_ARVALID_i is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -499,7 +499,7 @@
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -549,7 +549,7 @@
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -578,7 +578,7 @@
genvar k;
generate
for (k=0; k<N_COUNTERS; k=k+1) begin : generated_counter
always @(posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i) begin
always @(posedge S_AXI_ACLK_i) begin
if(!S_AXI_ARESETN_i)
slv_reg[k] <={C_S_AXI_DATA_WIDTH{1'b0}};
else begin
......@@ -801,6 +801,8 @@
.WEIGHTS_WIDTH (MCCU_WEIGHTS_WIDTH),
//Cores. Change this may break Verilator TB
.N_CORES (MCCU_N_CORES),
//Fault Tolerance
.FT(0),
//Signals per core. Change this may break Verilator TB
.CORE_EVENTS (MCCU_CORE_EVENTS)
)
......@@ -812,6 +814,8 @@
.quota_i (MCCU_quota_int),//One register per core
.update_quota_i (MCCU_update_quota_int),//Software map
.quota_o (MCCU_quota_o),//write back to a read register
.intr_FT1_o(),
.intr_FT2_o(),
.events_weights_i (MCCU_events_weights_int),//core_events times WEIGHTS_WIDTH registers
.interruption_quota_o (MCCU_int_o)//N_CORES output signals Add this to top or single toplevel interrupt and an interrupt vector that identifies the source?
// Individual interrupts allow each core to
......@@ -837,6 +841,7 @@
.events_i (events_int),//how to parametrize this? new parameter on top or up to the programer that does the integration?
.events_weights_i (MCCU_events_weights_int),//core_events times WEIGHTS_WIDTH registers
.interruption_rdc_o(intr_rdc_o),// interruption signaling a signal has exceed the expected maximum request time
.watermark_o(),
.interruption_vector_rdc_o(intrv_rdc_int) // vector with offending
//signals. One hot encoding.
//Cleared when MCCU is disabled.
......
......@@ -36,6 +36,8 @@
parameter integer N_SOC_EV = 32,
// Configuration registers
parameter integer N_CONF_REGS = 1,
// Fault tolerance mechanisms (FT==0 -> FT disabled)
parameter integer FT = 0,
//------------- Internal Parameters
......@@ -184,7 +186,11 @@
// MCCU interruption for exceeded quota. One signal per core
output wire [MCCU_N_CORES-1:0] intr_MCCU_o,
// RDC (Request Duration Counter) interruption for exceeded quota
output wire intr_RDC_o
output wire intr_RDC_o,
// FT (Fault tolerance) interrupt, error detected and recovered
output wire intr_FT1_o,
// FT (Fault tolerance) interrupt, error detected but not recoverable
output wire intr_FT2_o
);
//----------------------------------------------
// VIVADO: list of debug signals for ILA
......@@ -414,6 +420,7 @@ end
//----------------------------------------------
//TODO: What happen if we is active but no write is done to the range of the
//counters?
logic counters_fte2;
PMU_counters # (
.REG_WIDTH (REG_WIDTH),
.N_COUNTERS (N_COUNTERS)
......@@ -426,7 +433,8 @@ end
.we_i (wrapper_we_i),
.regs_i (counter_regs_int),
.regs_o (counter_regs_o),
.events_i (events_int)
.events_i (events_int),
.intr_FT2_o (counters_fte2)
);
//----------------------------------------------
......@@ -549,26 +557,16 @@ end
endcase
endgenerate
//register enable to solve Hazards
reg MCCU_rstn;
always @(posedge clk_i, negedge rstn_i) begin: MCCU_glitchless_rstn
if (!rstn_i) begin
MCCU_rstn <= 0;
end else begin
MCCU_rstn <= rstn_i && !MCCU_softrst;
end
end
//register enable to solve Hazards
reg MCCU_enable_int;
always @(posedge clk_i, negedge rstn_i) begin: MCCU_glitchless_enable
always @(posedge clk_i) begin: MCCU_glitchless_enable
if (!rstn_i) begin
MCCU_enable_int <= 0;
end else begin
MCCU_enable_int <= regs_i[BASE_MCCU_CFG][0];
end
end
logic MCCU_intr_FT1, MCCU_intr_FT2;
MCCU # (
// Width of data registers
.DATA_WIDTH (REG_WIDTH),
......@@ -576,18 +574,22 @@ end
.WEIGHTS_WIDTH (MCCU_WEIGHTS_WIDTH),
//Cores. Change this may break Verilator TB
.N_CORES (MCCU_N_CORES),
// Fault tolerance mechanisms (FT==0 -> FT disabled)
.FT (FT),
//Signals per core. Change this may break Verilator TB
.CORE_EVENTS (MCCU_N_EVENTS)
)
inst_MCCU(
.clk_i (clk_i),
.rstn_i (MCCU_rstn),//active low
.rstn_i (rstn_i && !MCCU_softrst),//active low
.enable_i (MCCU_enable_int),// Software map
.events_i (MCCU_events_int),
.quota_i (regs_i[BASE_MCCU_LIMITS:END_MCCU_LIMITS]),//One register per core
.update_quota_i (MCCU_update_quota_int),//Software map
.quota_o (regs_o[BASE_MCCU_QUOTA:END_MCCU_QUOTA]),//write back to a read register
.events_weights_i (MCCU_events_weights_int),//core_events times WEIGHTS_WIDTH registers
.intr_FT1_o (MCCU_intr_FT1),
.intr_FT2_o (MCCU_intr_FT2),
.interruption_quota_o (MCCU_intr_up)//N_CORES output signals Add this to top or single toplevel interrupt and an interrupt vector that identifies the source?
// Individual interrupts allow each core to
// handle their own interrupts , therefore
......@@ -608,9 +610,10 @@ end
assign regs_o[BASE_RDC_VECT][REG_WIDTH-1:MCCU_N_CORES*2] = '{default:0} ;
endgenerate
if (FT==0) begin
//register enable to solve Hazards
reg RDC_rstn;
always @(posedge clk_i, negedge rstn_i) begin: RDC_glitchless_rstn
always @(posedge clk_i) begin: RDC_glitchless_rstn
if (!rstn_i) begin
RDC_rstn <= 0;
end else begin
......@@ -618,10 +621,12 @@ end
RDC_rstn <= rstn_i && !regs_i[BASE_MCCU_CFG][MCCU_N_CORES+2+2];
end
end
//register enable to solve Hazards
// Does not nid replication since regs_i is already protected
// RDC_enable_int may be disabled for a single cycle but
// it will not be a permanent fault
reg RDC_enable_int;
always @(posedge clk_i, negedge rstn_i) begin: RDC_glitchless_enable
always @(posedge clk_i) begin: RDC_glitchless_enable
if (!rstn_i) begin
RDC_enable_int <= 0;
end else begin
......@@ -629,7 +634,6 @@ end
RDC_enable_int <= regs_i[BASE_MCCU_CFG][MCCU_N_CORES+2+1];
end
end
RDC #(
// Width of data registers
.DATA_WIDTH (REG_WIDTH),
......@@ -641,7 +645,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS)
) inst_RDC(
.clk_i (clk_i),
.rstn_i (RDC_rstn), //active low
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
......@@ -652,6 +656,160 @@ end
//maximum pulse length of a given core event
.watermark_o(MCCU_watermark_int)
);
end else begin : Rdctrip
//register enable to solve Hazards
// Does not nid replication since regs_i is already protected
// RDC_enable_int may be disabled for a single cycle but
// it will not be a permanent fault
logic RDC_enable_int_D, RDC_enable_int_Q;
logic RDC_enable_fte1, RDC_enable_fte2;
triple_reg#(.IN_WIDTH(1)
)RDC_enable_trip(
.clk_i(clk_i),
.rstn_i(rstn_i),
.din_i(RDC_enable_int_D),
.dout_o(RDC_enable_int_Q),
.error1_o(RDC_enable_fte1), // ignore corrected errors
.error2_o(RDC_enable_fte2)
);
always_comb begin
if (!rstn_i) begin
RDC_enable_int_D = 0;
end else begin
RDC_enable_int_D = regs_i[BASE_MCCU_CFG][6];
end
end
//Signals from instances to way3 voter
//inst
logic intr_RDC_ft0 ;
logic [MCCU_N_EVENTS-1:0] interruption_rdc_ft0 [0:MCCU_N_CORES-1];
logic [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_ft0 [0:MCCU_N_CORES-1]
[0:MCCU_N_EVENTS-1];
//inst1
logic intr_RDC_ft1 ;
logic [MCCU_N_EVENTS-1:0] interruption_rdc_ft1 [0:MCCU_N_CORES-1];
logic [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_ft1 [0:MCCU_N_CORES-1]
[0:MCCU_N_EVENTS-1];
//inst2
logic intr_RDC_ft2 ;
logic [MCCU_N_EVENTS-1:0] interruption_rdc_ft2 [0:MCCU_N_CORES-1];
logic [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_ft2 [0:MCCU_N_CORES-1]
[0:MCCU_N_EVENTS-1];
//FT error detected signals
//Even when the error is corrected latent faults may be present on this signals
// and software shall clear them
logic intr_RDC_fte1, interruption_rdc_fte1, MCCU_watermark_fte1;
logic intr_RDC_fte2, interruption_rdc_fte2, MCCU_watermark_fte2;
RDC #(
.DATA_WIDTH (REG_WIDTH),
.WEIGHTS_WIDTH (RDC_WEIGHTS_WIDTH),
.N_CORES (RDC_N_CORES),
.CORE_EVENTS (RDC_N_EVENTS)
) inst_RDC(
.clk_i (clk_i),
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
.interruption_rdc_o(intr_RDC_ft0),
.interruption_vector_rdc_o(interruption_rdc_ft0),
.watermark_o(MCCU_watermark_ft0)
);
RDC #(
.DATA_WIDTH (REG_WIDTH),
.WEIGHTS_WIDTH (RDC_WEIGHTS_WIDTH),
.N_CORES (RDC_N_CORES),
.CORE_EVENTS (RDC_N_EVENTS)
) inst1_RDC(
.clk_i (clk_i),
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
.interruption_rdc_o(intr_RDC_ft1),
.interruption_vector_rdc_o(interruption_rdc_ft1),
.watermark_o(MCCU_watermark_ft1)
);
RDC #(
.DATA_WIDTH (REG_WIDTH),
.WEIGHTS_WIDTH (RDC_WEIGHTS_WIDTH),
.N_CORES (RDC_N_CORES),
.CORE_EVENTS (RDC_N_EVENTS)
) inst2_RDC(
.clk_i (clk_i),
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
.interruption_rdc_o(intr_RDC_ft2),
.interruption_vector_rdc_o(interruption_rdc_ft2),
.watermark_o(MCCU_watermark_ft2)
);
// intr_RDC_ft
way3_voter #(
.IN_WIDTH(1)
)intr_RDC_way3(
.in0(intr_RDC_ft0),
.in1(intr_RDC_ft1),
.in2(intr_RDC_ft2),
.out(intr_RDC_o),
.error1_o(intr_RDC_fte1),
.error2_o(intr_RDC_fte2)
);
// interruption_rdc_ft
way3ua_voter #(
.W(MCCU_N_EVENTS),
.U(MCCU_N_CORES)
)interruption_rdc_way3(
.in0(interruption_rdc_ft0),
.in1(interruption_rdc_ft1),
.in2(interruption_rdc_ft2),
.out(interruption_rdc_o),
.error1_o(interruption_rdc_fte1),
.error2_o(interruption_rdc_fte2)
);
// MCCU_watermark_ft
way3u2a_voter #(
.W(MCCU_WEIGHTS_WIDTH),
.U(MCCU_N_CORES),
.D(MCCU_N_EVENTS)
)watermark_way3(
.in0(MCCU_watermark_ft0),
.in1(MCCU_watermark_ft1),
.in2(MCCU_watermark_ft2),
.out(MCCU_watermark_int),
.error1_o(MCCU_watermark_fte1),
.error2_o(MCCU_watermark_fte2)
);
end
//----------------------------------------------
//------------- Generate intr_FT_o
//----------------------------------------------
if (FT == 0 ) begin
assign intr_FT1_o = 1'b0;
assign intr_FT2_o = 1'b0;
end else begin
//Gather all the signals of corrected errors from FT scopes
// Codestyle. All scopes start with a capital letter
assign intr_FT1_o = |{
Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1,
Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1,
MCCU_intr_FT1
};
//Gather all the signals of uncorrected errors from FT scopes
// Codestyle. All scopes start with a capital letter
assign intr_FT2_o = |{
Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2,
Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2,
MCCU_intr_FT2,
counters_fte2
};
end
/////////////////////////////////////////////////////////////////////////////////
//
// Formal Verification section begins here.
......
......@@ -147,7 +147,7 @@ var struct packed{
assign slv_reg_Q = slv_reg;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
slv_reg<='{default:0};
end else begin
......@@ -186,7 +186,7 @@ always_comb begin
endcase
end
// address phase - register required inputs
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
//initialize all the structure to 0 at reset
address_phase <= '{default:0};
......@@ -217,7 +217,7 @@ always_ff @(posedge clk_i, negedge rstn_i) begin
end
//data phase - state update
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
state<=TRANS_IDLE;
end else begin
......
This diff is collapsed.
......@@ -3,4 +3,6 @@
!*.sh
!*.gtkw
!*.sby
seu_ip/hamming32t26d_dec/
seu_ip/hamming32t26d_enc/
seu_ip/way3_voter/
This diff is collapsed.
#$1
if [ -z "$1" ]
then
vlib MCCU
vmap work $PWD/MCCU
vlog +acc=rn +incdir+../../hdl/ ../../hdl/*.sv tb_MCCU.sv
vmake MCCU/ > Makefile
vsim work.tb_MCCU -do "view wave -new" -do "do wave.do" -do "run 40000"
else
vlib MCCU
vmap work $PWD/MCCU
vlog +acc=rn +incdir+../../hdl/ ../../hdl/*.sv tb_MCCU.sv
vmake MCCU/ > Makefile
vsim work.tb_MCCU $1 -do "do save_wave.do"
fi
......@@ -28,7 +28,7 @@
)
(
input wire clk_i,
//Active low asyncronous reset. It can have hardware or software source
//Active low syncronous reset. It can have hardware or software source
input wire rstn_i,
//Active high enable. If enabled MaxValue can increase and interruptions
//can be generated
......@@ -68,7 +68,7 @@
generate
for(x=0;x<N_CORES;x++) begin
for(y=0;y<CORE_EVENTS;y++) begin
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(!rstn_i)
max_value[CORE_EVENTS*x+y] <={WEIGHTS_WIDTH{1'b0}};
else begin
......@@ -104,7 +104,7 @@
endgenerate
//Register the output of comparison, to identify offending signal
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(!rstn_i)
interruption_vector_rdc_o <='{default:{CORE_EVENTS{1'b0}}};
else if (!enable_i)
......@@ -127,7 +127,7 @@
end
endgenerate
//Update past_interruption_rdc_o
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(!rstn_i)
past_interruption_rdc_o <= 1'b0;
else if (!enable_i)
......@@ -143,7 +143,7 @@
genvar q;
generate
for (q=0; q<N_COUNTERS; q=q+1) begin : generated_watermark
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(!rstn_i) begin
watermark_int[q] <={WEIGHTS_WIDTH{1'b0}};
end else begin
......@@ -192,7 +192,7 @@
for(y=0;y<CORE_EVENTS;y++) begin
assert property (max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}}
and events_i[x][y]==1 and enable_i |=>
max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}} or rstn_i);
max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}} or rstn_i==0);
end
end
......
......@@ -21,6 +21,8 @@ module PMU_counters #
(
// Width of registers data bus
parameter integer REG_WIDTH = 32,
// Fault tolerance mechanisms (FT==0 -> FT disabled)
parameter integer FT = 0,
// Amount of counters
parameter integer N_COUNTERS = 9
)
......@@ -47,7 +49,9 @@ module PMU_counters #
input wire [REG_WIDTH-1:0] regs_i [0:N_COUNTERS-1],
output logic [REG_WIDTH-1:0] regs_o [0:N_COUNTERS-1],
//external signals from Soc events
input wire [N_COUNTERS-1:0] events_i
input wire [N_COUNTERS-1:0] events_i,
// FT (Fault tolerance) interrupt, error detected but not recoverable
output wire intr_FT2_o
);
reg [REG_WIDTH-1:0] slv_reg [0:N_COUNTERS-1] /*verilator public*/;
wire [REG_WIDTH-1:0] adder_out [0:N_COUNTERS-1] /*verilator public*/;
......@@ -62,7 +66,7 @@ module PMU_counters #
generate
for (i=0; i<N_COUNTERS; i=i+1) begin
assign adder_out[i] = (events_i[i] & en_i)? slv_reg[i]+1:slv_reg[i];
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
slv_reg[i] <='{default:0};
end else begin
......@@ -88,7 +92,24 @@ module PMU_counters #
regs_o = adder_out;
end
end
//TODO: fill formal propperties
//FT mechanisms and intr
if(FT==0) begin
assign intr_FT2_o = 1'b0;
end else begin
//register last we_i in the negative and positive edges of clock
// For 200MHz, transients of width < 2500ps shall be detected
// For 500MHz, transients of width < 1000ps shall be detected
// Expected transients < 900ps
com_tr #(
.IN_WIDTH(1)
)dut_com_tr (
.clk_i(clk_i),
.dclk_i(~clk_i),
.rstn_i(rstn_i),
.signal_i(we_i),
.error_o(intr_FT2_o)
);
end
///////////////////////////////////////////////////////////////////////////////
//
// Formal Verification section begins here.
......
......@@ -56,7 +56,7 @@ module crossbar #
//Register output and assign muxes output
generate
for(x=0;x<N_OUT;x++) begin : reg_out
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if (!rstn_i) begin
vector_o[x] <= 0;
end else begin
......@@ -71,8 +71,7 @@ module crossbar #
//
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
assert(N_IN >= N_OUT);
// assert(N_IN >= N_OUT);
`endif
endmodule
......
......@@ -77,7 +77,7 @@ module PMU_overflow #
//hold the interruption vector until unit is reseted
logic [N_COUNTERS-1:0] past_intr_vect;
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
past_intr_vect<='{default:0};
end else begin
......
//-----------------------------------------------------
// DEPRECATED. DO NOT USE
//-----------------------------------------------------
// ProjectName: LEON3_kc705_pmu
// Function : Submodule of the PMU to handle quota consumption of a single
// core.
......@@ -87,7 +89,7 @@ module PMU_quota #
// state_int shall jump to reset state if the mask changes
wire new_mask;
reg [N_COUNTERS-1:0] old_mask;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
old_mask <= {N_COUNTERS{1'b0}};
end else if(softrst_i) begin
......@@ -106,7 +108,7 @@ module PMU_quota #
// ...
localparam N_BITS_STATES =$clog2(N_COUNTERS+1);
reg [N_BITS_STATES-1:0] state_int;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
integer i;
if(rstn_i == 1'b0 ) begin
state_int <={N_BITS_STATES{1'b0}};
......@@ -117,7 +119,7 @@ module PMU_quota #
//prevent overflow of statemachine
state_int <= 0;
end els