Merge branch 'jk/FT-rebase' into 'develop'

add fault tolerance

See merge request !11

.gitignore

+junk
 hdl/PMU_raw/
 *.swp
 hdl/tmp*
-
+*.questa.log
+*.lquesta.log

.gitmodules

+[submodule "tools/DAVOS"]
+	path = tools/DAVOS
+	url = https://github.com/GuillemCabo/DAVOS.git

LICENSE

 MIT License
 
-Copyright (c) 2021 CAOS_HW / HDL_IP
+Copyright (c) 2021 Barcelona Supercomputing Center (BSC-CNS)
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

README.md

@@ -4,7 +4,7 @@ This repository contains the RTL and documentation for the unit.
 
 
 *  The specs for each feature and memory map calculator can be found under the ```docs``` folder.
-*  Top levels for different configurations or wrappers are foun in ```rtl```.
-*  RTL for Submodules (MCCU, RDC, Counters, etc..) can be foun in ```submodules```.
+*  Top levels for different configurations or wrappers are found in ```rtl```.
+*  RTL for Submodules (MCCU, RDC, Counters, etc..) can be found in ```submodules```.
 *  Synth contains scripts for early area and frequency evaluation with yosys.
-*  ```tb``` contains testbenes and verification scripts.
\ No newline at end of file
+*  ```tb``` contains testbenches and verification scripts.

ci/.gitignore

@@ -2,3 +2,4 @@ AXI_PMU/
 tmp/
 pmu_ahb/
 \.*\.log
+.verilator.log

ci/lint.sh

@@ -14,7 +14,6 @@ rm -rf ./AXI_PMU
 ############
 ## TOP pmu_ahb.sv
 ############
-
 # Run Verilator
 printf "Please wait, running Verilator\n"
 verilator --lint-only ../hdl/pmu_ahb.sv \
@@ -24,7 +23,13 @@ verilator --lint-only ../hdl/pmu_ahb.sv \
 ../submodules/RDC/hdl/RDC.sv \
 ../submodules/quota/PMU_quota.sv \
 ../submodules/counters/PMU_counters.sv \
-../submodules/overflow/PMU_overflow.sv 2> $VERILATOR_LOG0
+../submodules/overflow/PMU_overflow.sv \
+../submodules/seu_ip/hamming32t26d_enc.sv \
+../submodules/seu_ip/hamming32t26d_dec.sv \
+../submodules/seu_ip/triple_reg.sv \
+../submodules/seu_ip/way3_voter.sv \
+../submodules/seu_ip/way3u2a_voter.sv \
+../submodules/seu_ip/way3ua_voter.sv 2> $VERILATOR_LOG0
 
 # Run Questa
 printf "Please wait, running Spyglass\n"
@@ -33,6 +38,13 @@ printf "Please wait, running Spyglass\n"
 ../submodules/crossbar/hdl/crossbar.sv \
 ../submodules/MCCU/hdl/MCCU.sv \
 ../submodules/RDC/hdl/RDC.sv \
+../submodules/overflow/PMU_overflow.sv \
+../submodules/seu_ip/hamming32t26d_enc.sv \
+../submodules/seu_ip/hamming32t26d_dec.sv \
+../submodules/seu_ip/triple_reg.sv \
+../submodules/seu_ip/way3_voter.sv \
+../submodules/seu_ip/way3u2a_voter.sv \
+../submodules/seu_ip/way3ua_voter.sv \
 ../submodules/quota/PMU_quota.sv \
 ../submodules/counters/PMU_counters.sv \
 ../submodules/overflow/PMU_overflow.sv 1> /dev/null 

ci/questa.sh

@@ -12,7 +12,9 @@ rm -f  $LOG
 # Go to target folder 
 cd ../tb/questa_sim/ || exit 1
 # Declare folders of tests to be executed
-declare -a StringArray=("tb_axi_pmu/" "tb_pmu_ahb/" "tb_pmu_raw/")
+declare -a StringArray=("tb_axi_pmu/" "tb_com_tr/" "tb_hamming16td11/" "tb_hamming32td26/" 
+                        "tb_pmu_ahb/" "tb_pmu_raw/" "tb_reg_sbf/" "tb_MCCU" "tb_crossbar"
+                        "tb_com_tr/")
 
 # Iterate the string array using for loop
 for val in ${StringArray[@]}; do

docs/.gitignore

+*.out
+*.toc
+*.gz
+*.aux
+*.log

docs/MCCU_specification/4-Section.tex

@@ -10,7 +10,7 @@
 		\hline
 		clk\_i & INPUT & 1 & - & Width of data registers & module port
 		\\
-		rstn\_i & INPUT & 1 & - & Active low asyncronous reset. It... & module port
+		rstn\_i & INPUT & 1 & - & Active low syncronous reset. It... & module port
 		\\
 		enable\_i & INPUT & 1 & - & can be generated & module port
 		\\

docs/RDC_specification/4-Section.tex

@@ -11,7 +11,7 @@
 		\hline
 		clk\_i & INPUT & 1 & - & Width of data registers & module port
 		\\
-		rstn\_i & INPUT & 1 & - & Active low asyncronous reset. It... & module port
+		rstn\_i & INPUT & 1 & - & Active low syncronous reset. It... & module port
 		\\
 		enable\_i & INPUT & 1 & - & can be generated & module port
 		\\

docs/fault_tolerance_ahbpmu/1-Section.tex

+\newpage
+\section{Overview}
+\label{chapter1}
+The SafePMU is capable of changing the execution of critical tasks, either if a control kernel is using  its measures to perform software control or by the use of interrupt service routines signaled by the unit. Given this scenario the unit shall be analyzed to detect possible failure modes. We focus our efforts on failures due to single event upsets (SEU) and single transient effects (SET) that can be mitigated at RTL level. Additional measures can be taken at a physical level such us the use of hardened memory cells on ASIC or periodical reconfiguration on FPGAs, but they shall be undertaken by the IP integrator in a project by project basis.\\
+Failure modes and fault tolerance measures have been analyzed for each RTL file. Common considerations among files and features are described under the general section.\\
+\begin{itemize}
+	\item \textbf{pmu\_ahb.sv:} Interface with AHB bus. Contains a PMU values and configuration registers, state machines for AHB control, combinational logic to manage register updates.
+	\item \textbf{PMU\_raw.sv:} Signal routing among instances, some signals with combinational logic for enables, IMPLEMENTATION OF SELFTEST MODE, registers RDC and MCCU signals.
+	\item \textbf{PMU\_counters.sv:} Internally registered counter values, combinational logic for adders and external update control.
+	\item \textbf{crossbar.sv:} Externally driven muxes and registered outputs.
+	\item \textbf{MCCU.sv:}Internally registered quotas. Capable of signaling interrupts.
+	\item \textbf{PMU\_overflow:} Mostly combinational with several internal registers. Interruption capable.
+	\item \textbf{RDC.sv:} Mainly combinational logic but it has several internal registers. Capable of signaling interrupts.\\
+\end{itemize}
+The following sections describe possible failure modes and potential mitigations. Each solution will result in a tradeoff between performance, resources, ease of use, and development time. Thus the recommended reliefs may change at a later date to match project goals.\\
\ No newline at end of file

docs/fault_tolerance_ahbpmu/3-Section.tex

+\newpage
+\section{Dependencies}
+\label{chapter3}
+\subsection{pmu\_ahb}
+Correct behavior depends on external AHB signals, event generators and \textit{PMU\_raw} outputs.
+\subsection{PMU\_raw}
+It depends on \textit{pmu\_ahb}, and assumes that registers driving the inputs are fault-tolerant to upsets. Outputs of the module are affected by the correct behavior of \textit{PMU\_counters}, \textit{PMU\_overflow}, \textit{MCCU}, and\textit{ PMU\_counters}. 
+\subsection{PMU\_counters}
+The module depends on the correctness of \textit{pmu\_ahb} configuration register \textit{slv\_reg} and glitchless propagation of all module inputs through\textit{ PMU\_raw}. 
+\subsection{Crossbar}
+The module depends on the correctness of \textit{pmu\_ahb} configuration register \textit{slv\_reg} and glitchless propagation of all module inputs through \textit{PMU\_raw}. 
+\subsection{MCCU}
+This module depends on the correctness of \textit{pmu\_ahb} configuration register \textit{slv\_re}g and glitchless propagation of all module inputs through \textit{PMU\_raw}. 
+\subsection{PMU\_overflow}
+This module depends on the correctness of \textit{pmu\_ahb} configuration register \textit{slv\_reg}. Glitchless propagation of all module inputs through \textit{PMU\_raw}, and correct behavior of \textit{PMU\_counters} is assumed.
+\subsection{RDC}
+This module depends on the correctness of \textit{pmu\_ahb} configuration register \textit{slv\_reg} and glitchless propagation of all module inputs through \textit{PMU\_raw}. 

docs/fault_tolerance_ahbpmu/4-Section.tex

+

docs/fault_tolerance_ahbpmu/5-Section.tex

+\newpage
+\section{Fault Tolerance IPs}
+\label{chapter5}
+\subsection{Parity encoder / decoder}
+
+\subsection{Hamming encoder / decoder}
+
+\subsection{Reed Solomon encoder / decoder}
+
+\subsection{Triple simultaneous voter}
+
+\subsection{Triple time delayed voter}
\ No newline at end of file

docs/fault_tolerance_ahbpmu/Makefile

+CC=pdflatex
+
+all: spec 
+
+spec: main.tex 1-Section.tex 2-Section.tex 3-Section.tex 4-Section.tex 5-Section.tex 6-Section.tex 7-Section.tex 8-Section.tex
+	$(CC) main.tex
+
+clean:
+	rm *.aux *.log *.blg *.bbl *.out
+
+clear:
+	rm *.aux *.log *.blg *.bbl *.out *.pdf 
+

docs/fault_tolerance_ahbpmu/main.tex

+
+% License:
+% CC BY-NC-SA 3.0 (http://creativecommons.org/licenses/by-nc-sa/3.0/)
+%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+%----------------------------------------------------------------------------------------
+%	PACKAGES AND OTHER DOCUMENT CONFIGURATIONS
+%----------------------------------------------------------------------------------------
+
+\documentclass[paper=a4, fontsize=11pt]{scrartcl} % A4 paper and 11pt font size
+
+\usepackage[T1]{fontenc} % Use 8-bit encoding that has 256 glyphs
+\usepackage{fourier} % Use the Adobe Utopia font for the document - comment this line to return to the LaTeX default
+\usepackage[english]{babel} % English language/hyphenation
+\usepackage{amsmath,amsfonts,amsthm} % Math packages
+\usepackage{lipsum} % Used for inserting dummy 'Lorem ipsum' text into the template
+
+\usepackage{caption}
+\usepackage{subcaption}
+\usepackage{graphicx}
+
+\usepackage{float}
+
+\usepackage{blindtext} %for enumarations
+
+\usepackage[]{hyperref}  %link collor
+
+%talbe layout to the right
+%\usepackage[labelfont=bf]{caption}
+%\captionsetup[table]{labelsep=space,justification=raggedright,singlelinecheck=off}
+%\captionsetup[figure]{labelsep=quad}
+
+\usepackage{sectsty} % Allows customizing section commands
+\allsectionsfont{\centering \normalfont\scshape} % Make all sections centered, the default font and small caps
+
+\usepackage{fancyhdr} % Custom headers and footers
+\usepackage{register} % Custom headers and footers
+\pagestyle{fancyplain} % Makes all pages in the document conform to the custom headers and footers
+\fancyhead{} % No page header - if you want one, create it in the same way as the footers below
+\fancyfoot[L]{} % Empty left footer
+\fancyfoot[C]{} % Empty center footer
+\fancyfoot[R]{\thepage} % Page numbering for right footer
+\renewcommand{\headrulewidth}{0pt} % Remove header underlines
+\renewcommand{\footrulewidth}{0pt} % Remove footer underlines
+\setlength{\headheight}{13.6pt} % Customize the height of the header
+
+\numberwithin{equation}{section} % Number equations within sections (i.e. 1.1, 1.2, 2.1, 2.2 instead of 1, 2, 3, 4)
+\numberwithin{figure}{section} % Number figures within sections (i.e. 1.1, 1.2, 2.1, 2.2 instead of 1, 2, 3, 4)
+\numberwithin{table}{section} % Number tables within sections (i.e. 1.1, 1.2, 2.1, 2.2 instead of 1, 2, 3, 4)
+
+%\setlength\parindent{0pt} % Removes all indentation from paragraphs - comment this line for an assignment with lots of text
+\usepackage{enumitem}
+\setenumerate[1]{label=\thesubsection.\arabic*.}
+\setenumerate[2]{label*=\arabic*.}
+\setlength\parskip{4pt}
+
+%----------------------------------------------------------------------------------------
+%	TITLE SECTION
+%----------------------------------------------------------------------------------------
+
+\newcommand{\horrule}[1]{\rule{\linewidth}{#1}} % Create horizontal rule command with 1 argument of height
+
+\title{	
+\normalfont \normalsize º
+\horrule{0.5pt} \\[0.4cm] % Thin top horizontal rule
+\huge  SafePMU Fault Tolerance Measures\\ % The assignment title
+\horrule{2pt} \\[0.5cm] % Thick bottom horizontal rule
+}
+
+\author{ Guillem Cabo Pitarch} % Your name
+
+\date{\today} % Today's date or a custom date
+
+\usepackage{listings}
+\lstdefinelanguage{VHDL}{
+	morekeywords={
+		library,use,all,entity,is,port,in,out,end,architecture,of,
+		begin,and
+	},
+	morecomment=[l]--
+}
+
+\usepackage{textcomp}
+\usepackage{xcolor}
+\colorlet{keyword}{blue!100!black!80}
+\colorlet{comment}{green!90!black!90}
+\lstdefinestyle{vhdl}{
+	language     = VHDL,
+	basicstyle   = \ttfamily,
+	keywordstyle = \color{keyword}\bfseries,
+	commentstyle = \color{comment},
+	framexleftmargin = 15pt
+}
+
+\usepackage{caption}
+\DeclareCaptionFont{white}{\color{white}}
+\DeclareCaptionFormat{listing}{%
+	\parbox{\textwidth}{\colorbox{gray}{\parbox{\textwidth}{#1#2#3}}\vskip-4pt}}
+\captionsetup[lstlisting]{format=listing,labelfont=white,textfont=white}
+\lstset{frame=lrb,xleftmargin=\fboxsep,xrightmargin=-\fboxsep}
+
+
+\begin{document}
+%\nocite{*}
+\maketitle % Print the title
+
+\newpage
+\tableofcontents
+
+%----------------------------------------------------------------------------------------
+%	Section 1
+%----------------------------------------------------------------------------------------
+
+\input{1-Section.tex}
+\input{2-Section.tex}
+\input{3-Section.tex}
+\input{4-Section.tex}
+\input{5-Section.tex}
+%----------------------------------------------------------------------------------------
+%	Section 2
+%----------------------------------------------------------------------------------------
+
+
+
+
+
+
+\end{document}

docs/fault_tolerance_ahbpmu/registers/tmp.txt

+--Crossbar
+
+\regfield{Output 6 [1:0]}{2}{30}{{00}}
+\regfield{Output 5}{5}{25}{{00}}
+\regfield{Output 4}{5}{20}{{00}}
+\regfield{Output 3}{5}{15}{{00}}
+\regfield{Output 2}{5}{10}{{00}}
+\regfield{Output 1}{5}{5}{{00}}
+\regfield{Output 0}{5}{0}{{00}}
+
+\regfield{Output 12[3:0]}{4}{28}{{00}}
+\regfield{Output 11}{5}{23}{{00}}
+\regfield{Output 10}{5}{18}{{00}}
+\regfield{Output 7}{5}{3}{{00}}
+\regfield{Output 9}{5}{13}{{00}}
+\regfield{Output 8}{5}{8}{{00}}
+\regfield{Output 6 [4:2]}{3}{0}{{00}}
+
+\regfield{Output 19 [0:0]}{1}{31}{{00}}
+\regfield{Output 18}{5}{26}{{00}}
+\regfield{Output 17}{5}{21}{{00}}
+\regfield{Output 16}{5}{16}{{00}}
+\regfield{Output 15}{5}{11}{{00}}
+\regfield{Output 14}{5}{6}{{00}}
+\regfield{Output 13}{5}{1}{{00}}
+\regfield{Output 12[4:4]}{1}{0}{{00}}
+
+\regfield{Reserved}{3}{29}{{x}}
+\regfield{Output 24}{5}{24}{{00}}
+\regfield{Output 23}{5}{19}{{00}}
+\regfield{Output 22}{5}{14}{{00}}
+\regfield{Output 21}{5}{9}{{00}}
+\regfield{Output 20}{5}{4}{{00}}
+\regfield{Output 19[4:1]}{4}{0}{{00}}
+
+--OVERFLOW
+
+\begin{register}{H}{Overflow interrupt enable mask}{0x064}
+	\label{over_cfg0}
+     \regfield{Reserved}{8}{24}{{x}}
+     \regfield{Input 23}{1}{23}{{00}}
+     \regfield{Input 22}{1}{22}{{00}}
+     \regfield{Input 21}{1}{21}{{00}}
+     \regfield{Input 20}{1}{20}{{00}}
+     \regfield{Input 19}{1}{19}{{00}}
+     \regfield{Input 18}{1}{18}{{00}}
+     \regfield{Input 17}{1}{17}{{00}}
+     \regfield{Input 16}{1}{16}{{00}}
+     \regfield{Input 15}{1}{15}{{00}}
+     \regfield{Input 14}{1}{14}{{00}}
+     \regfield{Input 13}{1}{13}{{00}}
+     \regfield{Input 12}{1}{12}{{00}}
+     \regfield{Input 11}{1}{11}{{00}}
+     \regfield{Input 10}{1}{10}{{00}}
+     \regfield{Input 9}{1}{9}{{00}}
+     \regfield{Input 8}{1}{8}{{00}}
+     \regfield{Input 7}{1}{7}{{00}}
+     \regfield{Input 6}{1}{6}{{00}}
+     \regfield{Input 5}{1}{5}{{00}}
+     \regfield{Input 4}{1}{4}{{00}}
+     \regfield{Input 3}{1}{3}{{00}}
+     \regfield{Input 2}{1}{2}{{00}}
+     \regfield{Input 1}{1}{1}{{00}}
+     \regfield{Input 0}{1}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+\begin{register}{H}{Overflow interrupt vector }{0x068}
+	\label{over_cfg1}
+     \regfield{Reserved}{8}{24}{{x}}
+     \regfield{Input 23}{1}{23}{{00}}
+     \regfield{Input 22}{1}{22}{{00}}
+     \regfield{Input 21}{1}{21}{{00}}
+     \regfield{Input 20}{1}{20}{{00}}
+     \regfield{Input 19}{1}{19}{{00}}
+     \regfield{Input 18}{1}{18}{{00}}
+     \regfield{Input 17}{1}{17}{{00}}
+     \regfield{Input 16}{1}{16}{{00}}
+     \regfield{Input 15}{1}{15}{{00}}
+     \regfield{Input 14}{1}{14}{{00}}
+     \regfield{Input 13}{1}{13}{{00}}
+     \regfield{Input 12}{1}{12}{{00}}
+     \regfield{Input 11}{1}{11}{{00}}
+     \regfield{Input 10}{1}{10}{{00}}
+     \regfield{Input 9}{1}{9}{{00}}
+     \regfield{Input 8}{1}{8}{{00}}
+     \regfield{Input 7}{1}{7}{{00}}
+     \regfield{Input 6}{1}{6}{{00}}
+     \regfield{Input 5}{1}{5}{{00}}
+     \regfield{Input 4}{1}{4}{{00}}
+     \regfield{Input 3}{1}{3}{{00}}
+     \regfield{Input 2}{1}{2}{{00}}
+     \regfield{Input 1}{1}{1}{{00}}
+     \regfield{Input 0}{1}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+--Quota
+Deprecated feature
+
+--MCCU
+\begin{register}{H}{MCCU main configuration}{0x074}
+	\label{MCCU_cfg}
+    \regfield{Reserved}{25}{8}{{x}}
+    \regfield{Soft reset RDC}{1}{7}{{0}}
+    \regfield{Enable RDC}{1}{6}{{0}}
+    \regfield{Update Quota Core 3}{1}{5}{{0}}
+    \regfield{Update Quota Core 2}{1}{4}{{0}}
+    \regfield{Update Quota Core 1}{1}{3}{{0}}
+    \regfield{Update Quota Core 0}{1}{2}{{0}}
+    \regfield{Soft reset MCCU}{1}{1}{{0}}
+    \regfield{Enable reset MCCU}{1}{0}{{0}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+\begin{figure}[H]
+	\begin{center}
+		\regfieldb{0x078}{32}{0}
+		\reglabelb{Core 0} \\
+		\regfieldb{0x07c}{32}{0}
+		\reglabelb{Core 1} \\
+		\regfieldb{0x080}{32}{0}
+		\reglabelb{Core 2} \\
+		\regfieldb{0x084}{32}{0}
+		\reglabelb{Core 3} \\
+		\end{center}
+	\caption{MCCU Quota limits for each core}\label{fig:MCCU_lim}
+\end{figure}
+
+\begin{figure}[H]
+	\begin{center}
+		\regfieldb{0x088}{32}{0}
+		\reglabelb{Core 0} \\
+		\regfieldb{0x08c}{32}{0}
+		\reglabelb{Core 1} \\
+		\regfieldb{0x090}{32}{0}
+		\reglabelb{Core 2} \\
+		\regfieldb{0x094}{32}{0}
+		\reglabelb{Core 3} \\
+		\end{center}
+	\caption{MCCU Current remaning Quota for each core}\label{fig:MCCU_ava}
+\end{figure}
+
+\begin{register}{H}{MCCU event weights register 0 (shared with RDC)}{0x098}
+	\label{MCCU_weight0}
+    \regfield{Input 3}{8}{24}{{00}}
+    \regfield{Input 2}{8}{16}{{00}}
+    \regfield{Input 1}{8}{8}{{00}}
+    \regfield{Input 0}{8}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+
+\begin{register}{H}{MCCU event weights register 1 (shared with RDC)}{0x09c}
+	\label{MCCU_weight1}
+    \regfield{Input 7}{8}{24}{{00}}
+    \regfield{Input 6}{8}{16}{{00}}
+    \regfield{Input 5}{8}{8}{{00}}
+    \regfield{Input 4}{8}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+--RDC
+
+\begin{register}{H}{RDC interrupt vector}{0x0a0}
+	\label{RDC_intrv}
+    \regfield{Reserved}{28}{4}{{x}}
+    \regfield{Core 3}{1}{3}{{00}}
+    \regfield{Core 2}{1}{2}{{00}}
+    \regfield{Core 1}{1}{1}{{00}}
+    \regfield{Core 0}{1}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+\begin{register}{H}{RDC event weights register 0 (shared with MCCU)}{0x098}
+	\label{RDC_weight0}
+    \regfield{Input 3}{8}{24}{{00}}
+    \regfield{Input 2}{8}{16}{{00}}
+    \regfield{Input 1}{8}{8}{{00}}
+    \regfield{Input 0}{8}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+
+\begin{register}{H}{RDC event weights register 1 (shared with MCCU)}{0x09c}
+	\label{RDC_weight1}
+    \regfield{Input 7}{8}{24}{{00}}
+    \regfield{Input 6}{8}{16}{{00}}
+    \regfield{Input 5}{8}{8}{{00}}
+    \regfield{Input 4}{8}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+\begin{register}{H}{RDC watermark register 0}{0x0a4}
+	\label{RDC_water0}
+    \regfield{Input 3}{8}{24}{{00}}
+    \regfield{Input 2}{8}{16}{{00}}
+    \regfield{Input 1}{8}{8}{{00}}
+    \regfield{Input 0}{8}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+
+
+\begin{register}{H}{RDC watermark register 1}{0x0a8}
+	\label{RDC_water1}
+    \regfield{Input 7}{8}{24}{{00}}
+    \regfield{Input 6}{8}{16}{{00}}
+    \regfield{Input 5}{8}{8}{{00}}
+    \regfield{Input 4}{8}{0}{{00}}
+	\reglabel{Reset value}\regnewline
+\end{register}
+