RDC stands by request duration counter. The purpose of this unit is track the length of a given event. At the core we assume that there are two types of events that are feed in to the PMU. On one hand there are single clock events, where each cycle that they are high means that a new event has occurred, and example of it would be instruction count for instance. On the other hand we have multiple-cycle events, in this case the event is risen at the begging of a given condition and remains high until the condition has finished, counting effectively the cycles that such condition is high rather than the number of events. An example of a multiple-cycle event would be the cache hold signal, that indicates the time the cache is waiting to get a response from memory.\\
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The RDC implements a mechanism to measure the length of multiple-cycle events and control that the length of a given event is not exceeded. If an event exceeds the set length an interruption is risen. A single interruption is provided for the whole unit.
This modules is meant to be instantiated by the interface agnostic PMU (PMU\_raw.sv). Only one instance of this module is required.
%This module is meant to be a blackbox inside the chisel code. It belongs to the Drac class in the \emph{rocket.scala} file. We can have as many instances of this module as cores are instantiated in the SoC. Currently only single core operation has been tested.
This unit uses several parameters. \textbf{DATA\_WIDTH} defines the size of the data registers.\\
\textbf{WEIGHTS\_WIDTH} defines the size of the registers that store the lengths of the requests and the maximum requests allowed.\textbf{ N\_CORES} is used to configured to replicate the internal logic of the RDC to support several cores. \textbf{CORE\_EVENTS} sets the number of events that are track for each core.\\
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Given the previous parameters the unit shall generate correct RTL without any manual modification to the source code.\\
The unit has a generate loop that will create for each input event of each core one counter, a max value hold register and update logic. While rstn\_is low the hold registers (max\_value) are set to 0.
If the unit is enabled and the event assigned to the counter is active the counter will increase by one and the result will be stored in the hold register. If the event is 0 the hold register is reset to 0.\\
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Each counter has overflow protection.
\subsection{Watermark}
The watermark logic assigns one register for each event of each core called watermark\_int. At reset the register is set to 0. If the unit is not enabled the values of watermark\_int are keept unchanged. If the unit is active the current value of watermark\_int is compared against the current value of the pulse counters (watermark\_int). When max\_value is larger than watermark\_int, the second is updated with the new value of the pulse counter (max\_value).\\
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\subsection{Interruption}
The RDC provides one interruption (interruption\_vector\_rdc\_o) for the whole unit an one interruption vector (interruption\_vector\_int) for each core. The interruption vector encodes in one hot encoding the signal exceeding the pulse width, the LSB of the vector is maps to the signal 0 of each core, and the remaining bits are filled in ascending order with the following signals.\\
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The interruption logic checks for each signal if its corresponding max\_value exceeds the respective events\_weights\_i. In other words if the current pulse been measured exceeds the weight currently assigned to it a bit in the interrupt vector of the corresponding core will be set to high.\\
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Interruptions are hold over time, until the init is disabled or reset. That is achieved by registering the output interruption vector (interruption\_vector\_rdc\_o) and applying an or operation between its past value and the current cycle internal interruption vector (interruption\_vector\_int).\\
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To decide if the RDC interruption needs to be risen all the interruption vectors are or-reduced along a bit that stores the previous state of the interrupt.
\subsection{Packages and structures}
No packages and structures are used in this module.
The interrupts shall be generated if the current pulse value is equal or larger than the event weigth. Otherwise if the event weight is set to the maximum value of the register, due to the overflow protection of the counters will prevent the interrupt to trigger, producing a non intuitive outcome. \\
