submodules for decoupled PMU

need for a PMU idependent from the AXI interface to port it in to other bus standards

hdl/PMU_counters.sv

+//-----------------------------------------------------
+// ProjectName: LEON3_kc705_pmu
+// Function   : Submodule of the PMU to handle counters 
+// Description: This module is contains the adders and registers for the PMU
+//              the registers are exposed through the interface to the modules
+//              other modules of the PMU and passed through to the PMU wrapper
+//              through the module PMU_raw
+//
+// Coder      : G.Cabo
+// References : 
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+`ifndef SYNT
+    `ifdef FORMAL 
+        `define ASSERTIONS
+    `endif
+`endif
+module PMU_counters #
+	(
+		// Width of registers data bus
+		parameter integer REG_WIDTH	= 32,
+		// Amount of counters
+		parameter integer N_COUNTERS	= 9
+	)
+	(
+		// Global Clock Signal
+		input wire  clk_i,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  rstn_i,
+		// Soft Reset Signal from configuration registeres. This Signal is 
+        // Active HIGH
+		input wire  softrst_i,
+		// Enable Signal from configuration registeres. This Signal is 
+        // Active HIGH
+		input wire  en_i,
+		// Write enable signal. When this signal is high any value in regs_i
+        // is feed in to the internal registers. The Wrapper has to  ensure
+        // that the propper values are feeded in.
+        // rst_i and softrst_i, have priority over we_i.
+        //TODO: Consider if is worth adding acces to individual registers
+		input wire  we_i,
+
+        // Input/output wire from registers of the wrapper to PMU_raw internal
+        // registers
+        input wire [REG_WIDTH-1:0] regs_i [0:N_COUNTERS-1],
+        output wire [REG_WIDTH-1:0] regs_o [0:N_COUNTERS-1],
+        //external signals from Soc events
+        input wire [N_COUNTERS-1:0] events_i 
+	);
+    reg [REG_WIDTH-1:0] slv_reg [0:N_COUNTERS-1] /*verilator public*/;
+//-------------Adders with reset
+    //Inside the generate loop it creates as many counters as the parameter
+    //N_COUNTERS. For each of them one slv_reg is assigned. When a soft reset
+    //(softrst_i high) or hard reset (rstn_i) slv_registers are set
+    //to 0. If non of this cases happen if the PMU is enabled (en_i high) and
+    //the event of the given counter (events_i[k]) is high the counter
+    // increases by one.
+    always @(posedge clk_i, negedge rstn_i) begin
+        integer i;
+        if(rstn_i == 1'b0 ) begin
+            for (i=0; i<N_COUNTERS; i=i+1) begin
+                slv_reg[i] <={REG_WIDTH{1'b0}};
+            end
+        end else begin
+            for (i=0; i<N_COUNTERS; i=i+1) begin
+                if(softrst_i) slv_reg[i] <={REG_WIDTH{1'b0}};
+                else if (we_i) slv_reg <= regs_i;
+                else if(events_i[i] & en_i) slv_reg[i] <= slv_reg[i]+1;
+            end
+        end
+    end
+//Map input and output registers
+    assign regs_o = slv_reg;
+//TODO: fill formal propperties
+////////////////////////////////////////////////////////////////////////////////
+//
+// Formal Verification section begins here.
+//
+////////////////////////////////////////////////////////////////////////////////
+`ifdef	FORMAL
+`endif
+
+endmodule
+
+`default_nettype wire //allow compatibility with legacy code and xilinx ip

hdl/PMU_overflow.sv

+//-----------------------------------------------------
+// ProjectName: LEON3_kc705_pmu
+// Function   : Submodule of the PMU to handle overflow of counters
+// Description: This module checks the bus of reg_o coming out of the counters
+//              module. It trigger the signal of overflow when all the bits of 
+//              a given bus are high.
+//
+//              The counters in the bus have one bit map in  to the overflow 
+//              interrupt mask. The index of the counter and the bit in the
+//              mask register is the same.
+//
+// Coder      : G.Cabo
+// References : 
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+`ifndef SYNT
+    `ifdef FORMAL 
+        `define ASSERTIONS
+    `endif
+`endif
+module PMU_overflow #
+	(
+		// Width of counters registers
+		parameter integer REG_WIDTH	= 32,
+		// Amount of counters
+		parameter integer N_COUNTERS	= 9
+	)
+	(
+		// Global Clock Signal
+		input wire  clk_i,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  rstn_i,
+        // Soft Reset Signal from configuration registeres. This Signal is 
+            // Active HIGH
+		input wire  softrst_i,
+		// Enable Signal from configuration registeres. This Signal is 
+            // Active HIGH
+		input wire  en_i,
+        // Input wire from wrapper containing the values of the counters
+        input wire [REG_WIDTH-1:0] counter_regs_i [0:N_COUNTERS-1],
+        // Input overflow interrupt mask. Only counters with their corresponding
+            // mask interrupt set to high can trigger the overflow interrupt
+            // If the mask is set to 0, the interrupt vector  mask will not be 
+            // updated either
+        input wire [N_COUNTERS-1:0] over_intr_mask_i, 
+        // Global interrupt overflow
+        output wire intr_overflow_o, 
+        // Output of the Overflow interruption vector
+        output wire [N_COUNTERS-1:0] over_intr_vect_o        
+	);
+//-------------Overflow
+    
+    //OR reduction to detect overflow of each counter
+    wire overflow [0:N_COUNTERS-1];
+    
+    genvar i;
+    generate
+        for (i=0; i<N_COUNTERS; i=i+1) begin : OR_reduction_counters
+            assign overflow[i]=|counter_regs_i[i];
+        end
+    endgenerate 
+    //check the mask for the overflow signals
+    wire [N_COUNTERS-1:0] masked_overflow ;
+    
+    generate 
+            for (i=0; i<N_COUNTERS; i=i+1) begin : masking_overflow
+                assign masked_overflow[i]=overflow[i] & over_intr_mask_i[i];
+            end
+    endgenerate
+    
+    //AND overflow and mask for each counter and OR reduc
+    wire intr_overflow_int;
+    assign intr_overflow_int=|masked_overflow;
+    //Drive output interrupt
+    assign intr_overflow_o = intr_overflow_int;
+    
+    //Set overflow internal interruption vector
+    reg [N_COUNTERS-1:0] over_intr_vect_int;
+    always_ff @(posedge clk_i, negedge rstn_i) begin
+        integer i;
+        if(rstn_i == 1'b0 ) begin
+                over_intr_vect_int <={N_COUNTERS{1'b0}};
+        end else begin
+            if(softrst_i) over_intr_vect_int <={N_COUNTERS{1'b0}};
+            else if(en_i) begin 
+                    over_intr_vect_int <=masked_overflow;
+            end
+        end
+    end
+    
+    //Drive output overflow interruption vector
+    assign over_intr_vect_o = over_intr_vect_int; 
+
+//TODO: fill formal propperties
+////////////////////////////////////////////////////////////////////////////////
+//
+// Formal Verification section begins here.
+//
+////////////////////////////////////////////////////////////////////////////////
+`ifdef	FORMAL
+`endif
+
+endmodule
+
+`default_nettype wire //allow compatibility with legacy code and xilinx ip
+