Commit 72775395 authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

change to sync reset

parent 8ae9a010
......@@ -10,7 +10,7 @@
\hline
clk\_i & INPUT & 1 & - & Width of data registers & module port
\\
rstn\_i & INPUT & 1 & - & Active low asyncronous reset. It... & module port
rstn\_i & INPUT & 1 & - & Active low syncronous reset. It... & module port
\\
enable\_i & INPUT & 1 & - & can be generated & module port
\\
......
......@@ -11,7 +11,7 @@
\hline
clk\_i & INPUT & 1 & - & Width of data registers & module port
\\
rstn\_i & INPUT & 1 & - & Active low asyncronous reset. It... & module port
rstn\_i & INPUT & 1 & - & Active low syncronous reset. It... & module port
\\
enable\_i & INPUT & 1 & - & can be generated & module port
\\
......
......@@ -244,7 +244,7 @@
// S_AXI_AWVALID_i and S_AXI_WVALID_i are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -278,7 +278,7 @@
// This process is used to latch the address when both
// S_AXI_AWVALID_i and S_AXI_WVALID_i are valid.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -299,7 +299,7 @@
// S_AXI_AWVALID_i and S_AXI_WVALID_i are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -331,7 +331,7 @@
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID_i && axi_awready && S_AXI_AWVALID_i;
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin : reset_all
......@@ -434,7 +434,7 @@
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i)
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -468,7 +468,7 @@
// The read address is also latched when S_AXI_ARVALID_i is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -499,7 +499,7 @@
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -549,7 +549,7 @@
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i )
always @( posedge S_AXI_ACLK_i)
begin
if ( S_AXI_ARESETN_i == 1'b0 )
begin
......@@ -578,7 +578,7 @@
genvar k;
generate
for (k=0; k<N_COUNTERS; k=k+1) begin : generated_counter
always @(posedge S_AXI_ACLK_i, negedge S_AXI_ARESETN_i) begin
always @(posedge S_AXI_ACLK_i) begin
if(!S_AXI_ARESETN_i)
slv_reg[k] <={C_S_AXI_DATA_WIDTH{1'b0}};
else begin
......
......@@ -551,7 +551,7 @@ end
//register enable to solve Hazards
reg MCCU_rstn;
always @(posedge clk_i, negedge rstn_i) begin: MCCU_glitchless_rstn
always @(posedge clk_i) begin: MCCU_glitchless_rstn
if (!rstn_i) begin
MCCU_rstn <= 0;
end else begin
......@@ -561,7 +561,7 @@ end
//register enable to solve Hazards
reg MCCU_enable_int;
always @(posedge clk_i, negedge rstn_i) begin: MCCU_glitchless_enable
always @(posedge clk_i) begin: MCCU_glitchless_enable
if (!rstn_i) begin
MCCU_enable_int <= 0;
end else begin
......@@ -610,7 +610,7 @@ end
//register enable to solve Hazards
reg RDC_rstn;
always @(posedge clk_i, negedge rstn_i) begin: RDC_glitchless_rstn
always @(posedge clk_i) begin: RDC_glitchless_rstn
if (!rstn_i) begin
RDC_rstn <= 0;
end else begin
......@@ -621,7 +621,7 @@ end
//register enable to solve Hazards
reg RDC_enable_int;
always @(posedge clk_i, negedge rstn_i) begin: RDC_glitchless_enable
always @(posedge clk_i) begin: RDC_glitchless_enable
if (!rstn_i) begin
RDC_enable_int <= 0;
end else begin
......
......@@ -147,7 +147,7 @@ var struct packed{
assign slv_reg_Q = slv_reg;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
slv_reg<='{default:0};
end else begin
......@@ -186,7 +186,7 @@ always_comb begin
endcase
end
// address phase - register required inputs
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
//initialize all the structure to 0 at reset
address_phase <= '{default:0};
......@@ -217,7 +217,7 @@ always_ff @(posedge clk_i, negedge rstn_i) begin
end
//data phase - state update
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
state<=TRANS_IDLE;
end else begin
......
......@@ -188,7 +188,7 @@ var struct packed{
logic [REG_WIDTH-1:0] slv_reg_D [0:N_REGS-1];
logic [REG_WIDTH-1:0] slv_reg_Q [0:N_REGS-1];
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
slv_reg<='{default:0};
end else begin
......@@ -231,7 +231,7 @@ always_comb begin
endcase
end
// address phase - register required inputs
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
//initialize all the structure to 0 at reset
address_phase <= '{default:0};
......@@ -260,7 +260,7 @@ always_ff @(posedge clk_i, negedge rstn_i) begin
end
//data phase - state update
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
state <= TRANS_IDLE;
end else begin
......
......@@ -31,7 +31,7 @@
)
(
input wire clk_i,
//Active low asyncronous reset. It can have hardware or software source
//Active low syncronous reset. It can have hardware or software source
input wire rstn_i,
//Active high enable. If enabled quota can decrease and interruptions
//can be generated
......@@ -81,7 +81,7 @@
integer i;
integer j;
// generate begin : GeneratedQuotaMonitor
always @(posedge clk_i, negedge rstn_i) begin: AsyncReset
always @(posedge clk_i) begin: syncReset
/*----------
Auxiliar variables
----------*/
......@@ -91,19 +91,19 @@
----------*/
if(rstn_i == 1'b0 ) begin
/*----------
Async reset Quota
sync reset Quota
----------*/
for (i=0; i<N_CORES; i=i+1) begin : ResetQuota
quota_int[i] <={DATA_WIDTH{1'b0}};
end
/*----------
Async reset current cycle consumed quota
sync reset current cycle consumed quota
----------*/
for (i=0; i<N_CORES; i=i+1) begin : ResetCCCQuota
ccc_suma_int[i] <={OVERFLOW_PROT{1'b0}};
end
/*----------
Async reset debug registers
sync reset debug registers
----------*/
`ifdef DEBUG
debug_ccc_suma_int <= {OVERFLOW_PROT{1'b0}};
......@@ -320,7 +320,7 @@ Section of Formal propperties, valid for SBY
the signal for a given weight is not active the current cycle.
--------------*/
//Auxiliar logic to compute sum of all signals and consumed quota
always@( posedge clk_i, negedge rstn_i ) begin
always@( posedge clk_i) begin
f_sum_weights =0; //initialize to 0 and add events_weights_int
if(rstn_i) begin // reset disabled
for (i=0; i<N_CORES; i=i+1) begin
......
......@@ -28,7 +28,7 @@
)
(
input wire clk_i,
//Active low asyncronous reset. It can have hardware or software source
//Active low syncronous reset. It can have hardware or software source
input wire rstn_i,
//Active high enable. If enabled MaxValue can increase and interruptions
//can be generated
......@@ -68,7 +68,7 @@
generate
for(x=0;x<N_CORES;x++) begin
for(y=0;y<CORE_EVENTS;y++) begin
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(!rstn_i)
max_value[CORE_EVENTS*x+y] <={WEIGHTS_WIDTH{1'b0}};
else begin
......@@ -104,7 +104,7 @@
endgenerate
//Register the output of comparison, to identify offending signal
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(!rstn_i)
interruption_vector_rdc_o <='{default:{CORE_EVENTS{1'b0}}};
else if (!enable_i)
......@@ -127,7 +127,7 @@
end
endgenerate
//Update past_interruption_rdc_o
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(!rstn_i)
past_interruption_rdc_o <= 1'b0;
else if (!enable_i)
......@@ -143,7 +143,7 @@
genvar q;
generate
for (q=0; q<N_COUNTERS; q=q+1) begin : generated_watermark
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(!rstn_i) begin
watermark_int[q] <={WEIGHTS_WIDTH{1'b0}};
end else begin
......
......@@ -62,7 +62,7 @@ module PMU_counters #
generate
for (i=0; i<N_COUNTERS; i=i+1) begin
assign adder_out[i] = (events_i[i] & en_i)? slv_reg[i]+1:slv_reg[i];
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
slv_reg[i] <='{default:0};
end else begin
......
......@@ -56,7 +56,7 @@ module crossbar #
//Register output and assign muxes output
generate
for(x=0;x<N_OUT;x++) begin : reg_out
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if (!rstn_i) begin
vector_o[x] <= 0;
end else begin
......
......@@ -77,7 +77,7 @@ module PMU_overflow #
//hold the interruption vector until unit is reseted
logic [N_COUNTERS-1:0] past_intr_vect;
always @(posedge clk_i, negedge rstn_i) begin
always @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
past_intr_vect<='{default:0};
end else begin
......
......@@ -87,7 +87,7 @@ module PMU_quota #
// state_int shall jump to reset state if the mask changes
wire new_mask;
reg [N_COUNTERS-1:0] old_mask;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
old_mask <= {N_COUNTERS{1'b0}};
end else if(softrst_i) begin
......@@ -106,7 +106,7 @@ module PMU_quota #
// ...
localparam N_BITS_STATES =$clog2(N_COUNTERS+1);
reg [N_BITS_STATES-1:0] state_int;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
integer i;
if(rstn_i == 1'b0 ) begin
state_int <={N_BITS_STATES{1'b0}};
......@@ -125,7 +125,7 @@ module PMU_quota #
localparam padding0 = max_width - REG_WIDTH;
reg [max_width-1:0] suma_int;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
integer i;
if(rstn_i == 1'b0 ) begin
suma_int <={max_width{1'b0}};
......@@ -144,7 +144,7 @@ module PMU_quota #
//Hold the state of the interruption
reg hold_intr_quota;
always_ff @(posedge clk_i, negedge rstn_i) begin
always_ff @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
hold_intr_quota <= 1'b0;
end else begin
......
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