Commit 725f52d6 authored by GuillemCabo's avatar GuillemCabo
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add PMU_raw spec

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\section{General purpose of the module}
PMU\_raw is an interface agnostic module that integrates all the features of the PMU based on the instance parameters. This module will instance the sub-modules that implement the MCCU, RDC, quota, counters and overflow when needed. Based on the input parameters it will generate the memory map of the PMU and each feature. This will allow to automatically connect most of the signals and extract the values of each parameter after elaboration to generate C drivers for the unit.\\
Given that the unit will act as a middle module between the features and the top level that will implement the control logic for the bus protocol of the SoC or Core that integrates the PMU, this module will pass through most of the signals.\\
In addition to the routing the unit implements a self-test feature that allows to bypass the event input and help to check that the software and hardware behave correctly.
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\section{Design placement}
This modules is meant to be instantiated by the interface specific PMU (pmu\ for instance). Only one instance of this module is required.
%This module is meant to be a blackbox inside the chisel code. It belongs to the Drac class in the \emph{rocket.scala} file. We can have as many instances of this module as cores are instantiated in the SoC. Currently only single core operation has been tested.
This unit has few external parameters.\textbf{REG\_WIDTH}, \textbf{N\_COUNTERS} and \textbf{N\_CONF\_REGS} are the basic parameters to configure the memory map of the PMU and route the signals. This parameters are provided by the module instancing the unit. A set of local parameters select the active features (\textbf{OVERFLOW}, \textbf{QUOTA}, \textbf{MCCU}, \textbf{RDC}).\\
Given the previous parameters all the memory map is generates as local parameters as well. For each group of signals associated with a feature function there is a local parameter with the name of the feature and function prefixed by \textbf{BASE\_}, \textbf{N\_} and \textbf{END\_}. This signals have the first register of the feature function, the number of used registers and the last register of the feature, respectively. The total of registers is stored in \textbf{TOTAL\_NREGS} and it adds up all the intermediate parameters with the registers used by each feature.\\
Is key to generate this parameters following a consistent method and build the values of the next parameters based in the last values to prevent inconsistencies. Furthermore all the parameters are important since the C libraries will be generated out of the parameter report generated by spyglass.
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\label{chapter 4}
Port Name & Direction & Width & Index & Comment & Comment Source
clk\_i & INPUT & 1 & - & Global Clock Signal & module port
rstn\_i & INPUT & 1 & - & Global Reset Signal. This Signal... & module port
regs\_i & INPUT & 896 & [0:27][31:0] & Input registers & module port
regs\_o & OUTPUT & 896 & [0:27][31:0] & Output registers & -\\
wrapper\_we\_i & INPUT & 1 & - & Write counters from regs\_i & module port
events\_i & INPUT & 9 & [8:0] & Event signals & module port
intr\_overflow\_o & OUTPUT & 1 & - & Overflow interruption & module port
intr\_quota\_o & OUTPUT & 1 & - & Quota interruption & module port
intr\_MCCU\_o & OUTPUT & 4 & [3:0] & MCCU interruption & module port
intr\_RDC\_o & OUTPUT & 1 & - & RDC interruption & module port
\caption{Ports of module PMU\_raw and default widths}
Interface signals of the module are listed in table \ref{port:PMU_raw}
% \centering
% \begin{tabular}{lllll}
% \hline
% Port\_Name & Direction & Width & Index & Description \\
% \hline
% CLK & INPUT & 1 & - & Main clock, up to 200MHz \\
% RST & INPUT & 1 & - & Hard reset. Active LOW \\
% SOFT\_RST & INPUT & 1 & - & Soft reset. Active LOW \\
% RESET\_ADDRESS & INPUT & 40 & - & Inital address of PC after soft or hard reset \\
% CSR\_RW\_RDATA & INPUT & 64 & - & - \\
% \end{tabular}
\section{Reset behavior}
The module contains a single global reset, called rstn\_i it is asynchronous and active low.\\
Any reset when active shall clear any internal register and set them to 0.\\
This unit will filter the reset signals of the MCCU, avoiding any glitch but making the reset synchronous.
\section{What could not happen}
No special restrictions have been considered other than specified in section \ref{behavior}.\\
ILA\_DEBUG\_PMU\_RAW shall be disabled unless the unit is under FPGA debug on a Xilinx platform.\\
FORMAL shall never be defined when doing synthesis.
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While the unit can be easily verified on simulations by feeding specific test patterns, on a hardware implementation is much harder to do without some hardware support. Self-test is important to verify that the software behaves correctly, but also to assure that there are no discrepancies with the simulation.\\
To perform a simple self-test the unit uses two bits of the configuration registers to change between four operation modes. \textbf{NO\_SELF\_TEST} (0b00), \textbf{ALL\_ACTIVE} (0b01), \textbf{ALL\_OFF} (0b10), \textbf{ONE\_ON} (0b11). This configuration modes allow, respectively, to pass through the events of the SoC, active all events, disable all events or active only event 0.\\
Events an I/O signals are passed through without changes.
Only active signals are passed through. If N\_COUNTERS larger than REG\_WIDTH it will need modifications to route \textbf{overflow\_intr\_mask\_i} and \textbf{overflow\_intr\_vect\_o}.
Only active signals are passed through. If N\_COUNTERS larger than REG\_WIDTH it will need modifications to route \textbf{quota\_mask\_i}.
Events are routed through an internal signal called \textbf{MCCU\_events\_int}. The MCCU will route part of the signals of the SoC, so the number of the counters can be smaller. It is defined by \textbf{MCCU\_N\_CORES} and \textbf{MCCU\_N\_EVENTS}.\\
Since the signal\textbf{MCCU\_softrst} may have glitches, \textbf{MCCU\_rstn} is synchronized to avoid such conditions and unpredictable resets on MCCU.\\
\textbf{MCCU\_update\_quota\_int},\textbf{MCCU\_events\_int}\textbf{MCCU\_events\_weights\_int} and \textbf{intr\_MCCU\_o} are not parametric. If a change is performed to MCCU\_N\_CORES or MCCU\_N\_EVENTS minor adjustmens will be required.
Only active signals are passed through. If N\_COUNTERS larger than REG\_WIDTH it will need modifications to route \textbf{interruption\_rdc\_o}. \\
The events and weight signals are shared with the MCCU. Therefore both functions must be present in the PMU or the MCCU code to route \textbf{MCCU\_events\_weights\_int} and \textbf{MCCU\_events\_weights\_int} shall be duplicated.
\subsection{Packages and structures}
No packages and structures are used in this module.
\section{Special cases, corner cases}
The interrupts shall be generated if the current pulse value is equal or larger than the event weigth. Otherwise if the event weight is set to the maximum value of the register, due to the overflow protection of the counters will prevent the interrupt to trigger, producing a non intuitive outcome. \\
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all: spec
spec: main.tex 1-Section.tex 2-Section.tex 3-Section.tex 4-Section.tex 5-Section.tex 6-Section.tex 7-Section.tex 8-Section.tex
$(CC) main.tex
rm *.aux *.log *.blg *.bbl *.out
rm *.aux *.log *.blg *.bbl *.out *.pdf
% License:
% CC BY-NC-SA 3.0 (
\documentclass[paper=a4, fontsize=11pt]{scrartcl} % A4 paper and 11pt font size
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\horrule{0.5pt} \\[0.4cm] % Thin top horizontal rule
\huge PMU\_raw specification version v1 \\ % The assignment title
\horrule{2pt} \\[0.5cm] % Thick bottom horizontal rule
\author{ Guillem Cabo Pitarch} % Your name
\date{\today} % Today's date or a custom date
\maketitle % Print the title
% Section 1
% Section 2
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