Commit 6a1ad51b authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

disable FV; tag as deprecated IP

fix FV RDC, Reset active low

wip fix FV asserts

remove proppery. With crossbar does not apply
parent 66ad5469
...@@ -537,20 +537,12 @@ end ...@@ -537,20 +537,12 @@ end
&& (hwrite_i==1) && (hwrite_i==1)
) )
|=> (ahb_write_req == 1) || rstn_i==0); |=> (ahb_write_req == 1) || rstn_i==0);
// If event 8 is low and current transaction is not a write, counter is
// stable
assert property ((events_i[8]==0 && $stable(events_i[8]) &&
ahb_write_req==0
)
|=> $stable(slv_reg[9]) ||
(slv_reg[9]==($past(slv_reg[9])+1))
|| $past(rstn_i)==1);
// If there is no write and no reset the slv_Regs used by the counters can // If there is no write and no reset the slv_Regs used by the counters can
// only decrease due to an overflow // only decrease due to an overflow
//posible resets of counters //posible resets of counters
sequence no_counter_reset; sequence no_counter_reset;
(rstn_i == 1) && (slv_reg[0][1] == 0); f_past_valid && ($past(rstn_i) != 0) && (slv_reg[0][1] == 0);
endsequence endsequence
sequence counter_reset; sequence counter_reset;
(rstn_i == 0) || (slv_reg[0][1] == 1); (rstn_i == 0) || (slv_reg[0][1] == 1);
...@@ -558,11 +550,11 @@ end ...@@ -558,11 +550,11 @@ end
//There is no pending write or it is not valid //There is no pending write or it is not valid
sequence no_ahb_write; sequence no_ahb_write;
//since ahb is pipelined i check for the last addres phase //since ahb is pipelined i check for the last addres phase
($past(hsel_i)==0) || ($past(hwrite_i)==0); f_past_valid && ($past(ahb_write_req==1'b0));
endsequence endsequence
//Register 1, assigned to counter 0 can't decrease //Register 1, assigned to counter 0 can't decrease
sequence no_decrease_counter(n); sequence no_decrease_counter(n);
slv_reg[n+1] >= $past(slv_reg[n+1]); (slv_reg[n+1] >= $past(slv_reg[n+1])) && f_past_valid;
endsequence endsequence
//Register 1, can decrease at overflow //Register 1, can decrease at overflow
sequence overflow_counter(n); sequence overflow_counter(n);
...@@ -580,11 +572,11 @@ end ...@@ -580,11 +572,11 @@ end
end end
endgenerate endgenerate
//Base configuration register remains stables if there isn't a reset or //Base configuration register remains stables if last cycle isn't a reset or
//write //write
assert property ( assert property (
no_ahb_write and no_counter_reset (ahb_write_req==1'b0) and (rstn_i==1)
|-> $stable(slv_reg_Q[0]) && $stable(pmu_regs_int[0]) && $stable(slv_reg[0]) |=> $stable(slv_reg[0])
); );
//TODO: If counters cant decrease by their own what explains that we read //TODO: If counters cant decrease by their own what explains that we read
......
...@@ -286,7 +286,7 @@ ...@@ -286,7 +286,7 @@
end end
end end
end end
assign interruption_quota_o[x] = enable_i? interruption_quota_q[x] : 1'b0; assign interruption_quota_o[x] = (enable_i && rstn_i) ? interruption_quota_q[x] : 1'b0;
end end
`ifdef ASSERTIONS `ifdef ASSERTIONS
...@@ -361,25 +361,54 @@ Section of Formal propperties, valid for SBY ...@@ -361,25 +361,54 @@ Section of Formal propperties, valid for SBY
* --------*/ * --------*/
//Interruption can be only high if consumed quota is larger than //Interruption can be only high if consumed quota is larger than
//available quota and the MCCU is enabled //available quota and the MCCU is enabled
integer k;
default clocking @(posedge clk_i); endclocking;
genvar k;
for(k=0;k<N_CORES;k++) begin
// If the unit is in reset or disabled the interrupts shall be 0 immediately.
assert property (
(f_past_valid && (rstn_i==0 || enable_i==0))
|->
(!interruption_quota_o[k])
);
// If an interrup is actrive it shall remain high unless there is a reset
assert property (
(f_past_valid && (interruption_quota_o[k]==1'b1))
|=>
($stable(interruption_quota_o[k]) || (!rstn_i || !enable_i))
);
/// If unit is not in reset or disabled. When quota_int[k]<ccc_suma_int[k] the interrupt
//shall rise in the next cycle
end
/*
always @(posedge clk_i) begin always @(posedge clk_i) begin
for(k=0;k<N_CORES;k++) begin for(k=0;k<N_CORES;k++) begin
if (f_past_valid) begin if (f_past_valid && rstn_i) begin
if ($past(quota_int[k]<ccc_suma_int[k]) && enable_i) begin if (($past(quota_int[k]<ccc_suma_int[k]) && enable_i)) begin
//The interruption shall be high //The interruption shall be high
assert(interruption_quota_o[k]==1'b1); assert(interruption_quota_[k]==1'b1);
//The interruption can only be high if the MCCU is enabled //The interruption can only be high if the MCCU is enabled
assert(interruption_quota_o[k]==enable_i); assert(interruption_quota_o[k]==enable_i);
end else begin end else begin
//interruption shall be disabled if not enabled //interruption shall be disabled if not enabled or unit in reset
if (enable_i== 0) begin if (enable_i== 0 || rstn_i==0) begin
assert(interruption_quota_o[k]==1'b0); assert(interruption_quota_o[k]==1'b0);
end else begin
//if the interrup was high, hold it high
if ($past(interruption_quota_o[k])==1'b1) begin
assert(interruption_quota_o[k]==1'b1);
end else begin
assert(interruption_quota_o[k]==1'b0);
end
end end
end end
end end
end end
end end
*/
`endif `endif
endmodule endmodule
`default_nettype wire //allow compatibility with legacy code and xilinx ip `default_nettype wire //allow compatibility with legacy code and xilinx ip
......
...@@ -192,7 +192,7 @@ ...@@ -192,7 +192,7 @@
for(y=0;y<CORE_EVENTS;y++) begin for(y=0;y<CORE_EVENTS;y++) begin
assert property (max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}} assert property (max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}}
and events_i[x][y]==1 and enable_i |=> and events_i[x][y]==1 and enable_i |=>
max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}} or rstn_i); max_value[CORE_EVENTS*x+y]=={WEIGHTS_WIDTH{1'b1}} or rstn_i==0);
end end
end end
......
//----------------------------------------------------- //-----------------------------------------------------
// DEPRECATED. DO NOT USE
//-----------------------------------------------------
// ProjectName: LEON3_kc705_pmu // ProjectName: LEON3_kc705_pmu
// Function : Submodule of the PMU to handle quota consumption of a single // Function : Submodule of the PMU to handle quota consumption of a single
// core. // core.
...@@ -167,6 +169,7 @@ module PMU_quota # ...@@ -167,6 +169,7 @@ module PMU_quota #
// //
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL `ifdef FORMAL
/*
//auxiliar registers //auxiliar registers
reg f_past_valid ; reg f_past_valid ;
initial f_past_valid = 1'b0; initial f_past_valid = 1'b0;
...@@ -186,6 +189,7 @@ module PMU_quota # ...@@ -186,6 +189,7 @@ module PMU_quota #
cover property (((quota_limit_i==5)[*5] |-> (intr_quota_o==1))); cover property (((quota_limit_i==5)[*5] |-> (intr_quota_o==1)));
// Set all the the events in the mask to one and keep it stable // Set all the the events in the mask to one and keep it stable
cover property ((quota_mask_i== {N_COUNTERS{1'b1}})[*5] |-> (intr_quota_o==1)); cover property ((quota_mask_i== {N_COUNTERS{1'b1}})[*5] |-> (intr_quota_o==1));
*/
// Roll over the max value of suma_int // Roll over the max value of suma_int
/* /*
cover property (($past(suma_int)=={max_width{1'b1}}) cover property (($past(suma_int)=={max_width{1'b1}})
...@@ -204,6 +208,7 @@ module PMU_quota # ...@@ -204,6 +208,7 @@ module PMU_quota #
*/ */
// The interruption can't fall once it is risen unless the unit is // The interruption can't fall once it is risen unless the unit is
// softreset // softreset
/*
assert property ($rose(intr_quota_o) |-> ($past(softrst_i)||$past(rstn_i))); assert property ($rose(intr_quota_o) |-> ($past(softrst_i)||$past(rstn_i)));
// The interruption shall be high eventually // The interruption shall be high eventually
assert property (##[0:$] intr_quota_o ); assert property (##[0:$] intr_quota_o );
...@@ -214,7 +219,7 @@ module PMU_quota # ...@@ -214,7 +219,7 @@ module PMU_quota #
// use all inputs. Roll over all the states of the addition once before // use all inputs. Roll over all the states of the addition once before
// trigger an interrupt // trigger an interrupt
//TODO //TODO
*/
`endif `endif
endmodule endmodule
......
[*] [*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jun 19 15:40:08 2020 [*] Mon Jun 14 16:13:35 2021
[*] [*]
[dumpfile] "/home/bscuser/BSC/grlib-gpl-2019-4-b4246-kc705/lib/bsc/ahb_pmu/bsc_pmu/tb/formal/pmu_ahb_sby/pmu_ahb/engine_1/trace.vcd" [dumpfile] "/home/gcabo/BSC/bsc_pmu/tb/formal/pmu_ahb_sby/pmu_ahb_bmc/engine_1/trace.vcd"
[dumpfile_mtime] "Fri Jun 19 15:34:43 2020" [dumpfile_mtime] "Mon Jun 14 16:08:49 2021"
[dumpfile_size] 84191 [dumpfile_size] 154453
[savefile] "/home/bscuser/BSC/grlib-gpl-2019-4-b4246-kc705/lib/bsc/ahb_pmu/bsc_pmu/tb/formal/pmu_ahb_sby/pmu_ahb.gtkw" [savefile] "/home/gcabo/BSC/bsc_pmu/tb/formal/pmu_ahb_sby/pmu_ahb.gtkw"
[timestart] 0 [timestart] 0
[size] 1920 1025 [size] 1853 1025
[pos] 22 22 [pos] 22 22
*-3.707499 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-3.707499 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] pmu_ahb. [treeopen] pmu_ahb.
[treeopen] pmu_ahb.inst_pmu_raw.
[sst_width] 228 [sst_width] 228
[signals_width] 548 [signals_width] 548
[sst_expanded] 1 [sst_expanded] 1
...@@ -19,10 +18,8 @@ ...@@ -19,10 +18,8 @@
@28 @28
[color] 1 [color] 1
(30)pmu_ahb.slv_reg<1>[31:0] (30)pmu_ahb.slv_reg<1>[31:0]
@29
[color] 1 [color] 1
pmu_ahb.rstn_i pmu_ahb.rstn_i
@28
[color] 2 [color] 2
pmu_ahb.hsel_i pmu_ahb.hsel_i
[color] 2 [color] 2
...@@ -99,9 +96,6 @@ pmu_ahb.slv_reg<1>[31:0] ...@@ -99,9 +96,6 @@ pmu_ahb.slv_reg<1>[31:0]
-group_end -group_end
@28 @28
pmu_ahb.inst_pmu_raw.clk_i pmu_ahb.inst_pmu_raw.clk_i
@22
pmu_ahb.inst_pmu_raw.events_i[8:0]
@28
pmu_ahb.hburst_i[2:0] pmu_ahb.hburst_i[2:0]
pmu_ahb.hmastlock_i pmu_ahb.hmastlock_i
@22 @22
...@@ -291,19 +285,8 @@ pmu_ahb.slv_reg<9>[31:0] ...@@ -291,19 +285,8 @@ pmu_ahb.slv_reg<9>[31:0]
@28 @28
[color] 7 [color] 7
pmu_ahb.ahb_write_req pmu_ahb.ahb_write_req
@800022 @800200
pmu_ahb.inst_pmu_raw.events_i[8:0] -pmu_ahb.inst_pmu_raw.events_i
@28
[color] 7
(0)pmu_ahb.inst_pmu_raw.events_i[8:0]
(1)pmu_ahb.inst_pmu_raw.events_i[8:0]
(2)pmu_ahb.inst_pmu_raw.events_i[8:0]
(3)pmu_ahb.inst_pmu_raw.events_i[8:0]
(4)pmu_ahb.inst_pmu_raw.events_i[8:0]
(5)pmu_ahb.inst_pmu_raw.events_i[8:0]
(6)pmu_ahb.inst_pmu_raw.events_i[8:0]
(7)pmu_ahb.inst_pmu_raw.events_i[8:0]
(8)pmu_ahb.inst_pmu_raw.events_i[8:0]
@1001200 @1001200
-group_end -group_end
@c00200 @c00200
...@@ -384,317 +367,16 @@ pmu_ahb.slv_reg_Q<9>[31:0] ...@@ -384,317 +367,16 @@ pmu_ahb.slv_reg_Q<9>[31:0]
@28 @28
pmu_ahb.inst_pmu_raw.inst_counters.clk_i pmu_ahb.inst_pmu_raw.inst_counters.clk_i
pmu_ahb.inst_pmu_raw.inst_counters.en_i pmu_ahb.inst_pmu_raw.inst_counters.en_i
@800022 @800200
pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0] -pmu_ahb.inst_pmu_raw.inst_counters.events_i
@28
(0)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(1)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(2)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(3)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(4)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(5)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(6)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(7)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
(8)pmu_ahb.inst_pmu_raw.inst_counters.events_i[8:0]
@1001200 @1001200
-group_end -group_end
@28 @28
pmu_ahb.inst_pmu_raw.inst_counters.f_past_valid pmu_ahb.inst_pmu_raw.inst_counters.f_past_valid
@c00022 @c00200
pmu_ahb.inst_pmu_raw.inst_counters.regs_i[287:0] -pmu_ahb.inst_pmu_raw.inst_counters.regs_i
@28
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