Commit 66ad5469 authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

disable intr mccu while disabled, fix FV asserts

parent 17bd62e5
...@@ -279,12 +279,16 @@ ...@@ -279,12 +279,16 @@
if(rstn_i == 1'b0 ) begin if(rstn_i == 1'b0 ) begin
interruption_quota_q[x] <= 1'b0; interruption_quota_q[x] <= 1'b0;
end else begin end else begin
if(enable_i) begin
interruption_quota_q[x] <= interruption_quota_d[x] | interruption_quota_q[x]; interruption_quota_q[x] <= interruption_quota_d[x] | interruption_quota_q[x];
end else begin
interruption_quota_q[x] <= 1'b0;
end
end end
end end
assign interruption_quota_o[x] = enable_i? interruption_quota_q[x] : 1'b0;
end end
assign interruption_quota_o = interruption_quota_q;
`ifdef ASSERTIONS `ifdef ASSERTIONS
always @(posedge clk_i) begin always @(posedge clk_i) begin
for(integer x=0; x<N_CORES; x=x+1) begin: InterruptionQuota for(integer x=0; x<N_CORES; x=x+1) begin: InterruptionQuota
...@@ -319,10 +323,10 @@ Section of Formal propperties, valid for SBY ...@@ -319,10 +323,10 @@ Section of Formal propperties, valid for SBY
end end
/*-------------- /*--------------
When reset (rstn_i)is active all internal registers shall be set to 0 in When reset (rstn_i)is active all internal registers shall be set to 0 in
the same cycle. the next cycle.
--------------*/ --------------*/
always @(*) begin always @(posedge clk_i) begin
if(0 == rstn_i) begin if(0 == $past(rstn_i) && f_past_valid) begin
assert(0 == quota_int.sum()); assert(0 == quota_int.sum());
assert(0 == ccc_suma_int.sum()); assert(0 == ccc_suma_int.sum());
end end
...@@ -345,15 +349,11 @@ Section of Formal propperties, valid for SBY ...@@ -345,15 +349,11 @@ Section of Formal propperties, valid for SBY
end end
end end
end end
//assert that the addition of quotas consumed in the current cycle is 0 at //assert that the addition of quotas consumed in the current cycle
//reset or equal to the internal weights. //equal to the internal weights.
always @(posedge clk_i) begin always @(posedge clk_i) begin
if(rstn_i) begin if(rstn_i) begin
assert(f_sum_weights == ccc_suma_int.sum()); assert(f_sum_weights == ccc_suma_int.sum());
end else begin
//This assertion is redundant but I left it here for help with
//understanding the previous assertion
assert(0 ==ccc_suma_int.sum());
end end
end end
/*--------- /*---------
...@@ -362,20 +362,23 @@ Section of Formal propperties, valid for SBY ...@@ -362,20 +362,23 @@ Section of Formal propperties, valid for SBY
//Interruption can be only high if consumed quota is larger than //Interruption can be only high if consumed quota is larger than
//available quota and the MCCU is enabled //available quota and the MCCU is enabled
integer k; integer k;
always @(*) begin always @(posedge clk_i) begin
for(k=0;k<N_CORES;k++) begin for(k=0;k<N_CORES;k++) begin
if (quota_int[k]<ccc_suma_int[k] && enable_i) begin if (f_past_valid) begin
if ($past(quota_int[k]<ccc_suma_int[k]) && enable_i) begin
//The interruption shall be high //The interruption shall be high
assert(interruption_quota_o[k]==1'b1); assert(interruption_quota_o[k]==1'b1);
//The interruption can only be high if the MCCU is enabled //The interruption can only be high if the MCCU is enabled
assert(interruption_quota_o[k]==enable_i); assert(interruption_quota_o[k]==enable_i);
end else begin end else begin
//interruption shall be disabled regardless of enable_i //interruption shall be disabled if not enabled
//TODO: if we retain the previous state (hold interrupt) this does not apply if (enable_i== 0) begin
assert(interruption_quota_o[k]==1'b0); assert(interruption_quota_o[k]==1'b0);
end end
end end
end end
end
end
`endif `endif
endmodule endmodule
......
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