Commit 5f1fb9b7 authored by Guillem's avatar Guillem
Browse files

WIP: connect MCCU within PMU

non usable yet
parent fc060a83
# Hierarchy
+ AXI_PMU.v
+ AXI_PMU_interface_v1_0_S00_AXI.sv
+ MCCU.sv
# Parameters
### AXI_PMU.v
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| C_S_AXI_DATA_WIDTH | 32 | 32/64 | Sets the data width of the bus |
| C_S_AXI_ADDR_WIDTH | 7 | integer | Defines the bits needed by the peripheral to addres internal registers |
### AXI_PMU_interface_v1_0_S00_AXI.sv
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| C_S_AXI_DATA_WIDTH | 32 | 32/64 | Sets the data width of the bus |
| C_S_AXI_ADDR_WIDTH | 7 | integer | Defines the bits needed by the peripheral to addres internal registers |
| N_COUNTERS | 9 | integer | Configures the amount of counters and input signals of the unit |
| N_CONF_REGS | 1 | integer | Sets the amount of configuration registers that are acessible by internal hardware |
| OVERFLOW | 1 | bool | Instantiates the hardware required to detect overflows and trigger an overflow interrupt |
| QUOTA | 1 | bool | Instantiates the hardware for quota monitoring and quota interrupt |
| MCCU | 1 | bool | MCCU - Maximum-contention Control Unit mode |
| N_CORES | 1 | integer[1-4] | MCCU - Number of cores to track |
### MCCU.sv
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| DATA_WIDTH | 32 | 32/64 | Width of data registers |
| WEIGHTS_WIDTH | 7 | integer | Width of weights registers |
| N_CORES | 4 | integer[1-4] | MCCU - Number of cores to track |
| CORE_EVENTS | 4 | integer[1-16] | Signals per core |
| OVERFLOW_PROT | DATA_WIDTH * 2| integer | Size of accumulation registers|
| O_D_0PAD | OVERFLOW_PROT - DATA_WIDTH) | Padding of 0s for overflow and data|
| D_W_0PAD | DATA_WIDTH - WEIGHTS_WIDTH) | Padding of 0s for weights and data|
| O_W_0PAD | OVERFLOW_PROT - WEIGHTS_WIDTH| Padding of 0s for overflow and weights|
# Pinout
### AXI_PMU.v
| Number | Name | Type | Bus_wide(bits) |
|--------|---------------|------|------------------|
| 1 | int_quota_c0_o| out | 1 |
| 2 | int_quota_c1_o| out | 1 |
| 3 | int_overflow_o| out | 1 |
| 4 | int_quota_o | out | 1 |
| 5 | EV0_i | in | 1 |
| 6 | EV1_i | in | 1 |
| 7 | EV2_i | in | 1 |
| 8 | EV3_i | in | 1 |
| 9 | EV4_i | in | 1 |
| 10 | EV5_i | in | 1 |
| 11 | EV6_i | in | 1 |
| 12 | EV7_i | in | 1 |
| 13 | EV8_i | in | 1 |
| 14 | EV9_i | in | 1 |
| 15 | EV10_i | in | 1 |
| 16 | EV11_i | in | 1 |
| 17 | EV12_i | in | 1 |
| 18 | EV13_i | in | 1 |
| 19 | EV14_i | in | 1 |
| 20 | EV15_i | in | 1 |
| 21 | S_AXI_ACLK_i | in | C_S_AXI_DATA_WIDTH |
| 22 | S_AXI_ARESETN_i | in | C_S_AXI_DATA_WIDTH |
| 23 | S_AXI_AWADDR_i | in | C_S_AXI_DATA_WIDTH |
| 24 | S_AXI_AWVALID_i | in | C_S_AXI_DATA_WIDTH |
| 25 | S_AXI_AWREADY_o | out | C_S_AXI_DATA_WIDTH |
| 26 | S_AXI_WDATA_i | in | C_S_AXI_DATA_WIDTH |
| 27 | S_AXI_WSTRB_i | in | C_S_AXI_DATA_WIDTH |
| 28 | S_AXI_WVALID_i | in | C_S_AXI_DATA_WIDTH |
| 29 | S_AXI_WREADY_o | out | C_S_AXI_DATA_WIDTH |
| 30 | S_AXI_BRESP_o | out | C_S_AXI_DATA_WIDTH |
| 31 | S_AXI_BVALID_o | out | C_S_AXI_DATA_WIDTH |
| 32 | S_AXI_BREADY_i | in | C_S_AXI_DATA_WIDTH |
| 33 | S_AXI_ARADDR_i | in | C_S_AXI_DATA_WIDTH |
| 34 | S_AXI_ARVALID_i | in | C_S_AXI_DATA_WIDTH |
| 35 | S_AXI_ARREADY_o | out | C_S_AXI_DATA_WIDTH |
| 36 | S_AXI_RDATA_o | out | C_S_AXI_DATA_WIDTH |
| 37 | S_AXI_RRESP_o | out | C_S_AXI_DATA_WIDTH |
| 38 | S_AXI_RVALID_o | out | C_S_AXI_DATA_WIDTH |
| 39 | S_AXI_RREADY_i | in | C_S_AXI_DATA_WIDTH |
### AXI_PMU_interface_v1_0_S00_AXI.sv
| Number | Name | Type | Bus_wide(bits) |
|--------|---------------|------|------------------|
| 1 | MCCU_int_o | out | N_CORES |
| 2 | int_overflow_o| out | 1 |
| 3 | int_quota_o | out | 1 |
| 4 | events_i | in | N_COUNTERS |
| 5 | S_AXI_ACLK_i | in | C_S_AXI_DATA_WIDTH |
| 6 | S_AXI_ARESETN_i | in | C_S_AXI_DATA_WIDTH |
| 7 | S_AXI_AWADDR_i | in | C_S_AXI_DATA_WIDTH |
| 8 | S_AXI_AWPROT_i | in | C_S_AXI_DATA_WIDTH |
| 9 | S_AXI_AWVALID_i | in | C_S_AXI_DATA_WIDTH |
| 10 | S_AXI_AWREADY_o | out | C_S_AXI_DATA_WIDTH |
| 11 | S_AXI_WDATA_i | in | C_S_AXI_DATA_WIDTH |
| 12 | S_AXI_WSTRB_i | in | C_S_AXI_DATA_WIDTH |
| 13 | S_AXI_WVALID_i | in | C_S_AXI_DATA_WIDTH |
| 14 | S_AXI_WREADY_o | out | C_S_AXI_DATA_WIDTH |
| 15 | S_AXI_BRESP_o | out | C_S_AXI_DATA_WIDTH |
| 16 | S_AXI_BVALID_o | out | C_S_AXI_DATA_WIDTH |
| 17 | S_AXI_BREADY_i | in | C_S_AXI_DATA_WIDTH |
| 18 | S_AXI_ARADDR_i | in | C_S_AXI_DATA_WIDTH |
| 19 | S_AXI_ARPROT_i | in | C_S_AXI_DATA_WIDTH |
| 20 | S_AXI_ARVALID_i | in | C_S_AXI_DATA_WIDTH |
| 21 | S_AXI_ARREADY_o | out | C_S_AXI_DATA_WIDTH |
| 22 | S_AXI_RDATA_o | out | C_S_AXI_DATA_WIDTH |
| 23 | S_AXI_RRESP_o | out | C_S_AXI_DATA_WIDTH |
| 24 | S_AXI_RVALID_o | out | C_S_AXI_DATA_WIDTH |
| 25 | S_AXI_RREADY_i | in | C_S_AXI_DATA_WIDTH |
### MCCU.sv
| Number | Name | Type | width(default) |index |
|--------|--------------- |------|------------------|
| 1 | clk_i | in | 1 | |
| 2 | rst_i | in | 1 | |
| 3 | enable_i | in | 1 | |
| 4 | events_i | in | 16 |packed [CORE_EVENTS-1:0] unpacked [0:N_CORES-1] |
| 5 | quota_i | in | 128 |packed [DATA_WIDTH-1:0] unpacked [0:N_CORES-1] |
| 6 | update_quota_i | in | 4 |[0:N_CORES-1] |
| 7 | quota_o | out | 128 |packed [DATA_WIDTH-1:0] unpacked [0:N_CORES-1] |
| 8 | events_weights_i | in | 112 |packed [WEIGHTS_WIDTH-1:0] unpacked [0:N_CORES-1][0:CORE_EVENTS-1] |
| 9 | interruption_quota_o | out | 4 |[N_CORES-1:0] |
===========================================================================================================
# Memory map
### MCCU.sv
Pass down to AXI_PMU_interface_v1_0_S00_AXI.sv
### AXI_PMU_interface_v1_0_S00_AXI.sv
| Memory offset (HEX) | Register | Name | Function |
| :---: | :----: | :---: | :---:|
| 0 | 0 | Cnt\_0 | Contains total of events have been generated by EV0 since last reset|
| ... | ... | ... | ... |
| 0x3C | 15 | Cnt\_15 | Contains total of events have been generated by EV15 since last reset|
| 0x40 | 16 | main\_cfg | control over software reset and enable |
| 0x44 | 17 | aux\_cfg\_0 | Configuration for future features|
| ... | ... | ... | ... |
| 0x50 | 20 | aux\_cfg\_3 | Configuration for future features |
| 0x54 | 21 | Overflow | Overflow flags of each counter|
| 0x58 | 22 | Quota\_mask | User defined mask that selects which signals must be acounted for the quota|
| 0x5E | 23 | Quota\_limit | User defined value. When quota is over this value int\_quota is triggered |
### AXI_PMU.v
......@@ -53,9 +53,14 @@
input wire EV13_i ,// signal
input wire EV14_i ,// signal
input wire EV15_i ,// signal
//outputs
output wire int_overflow_o,
output wire int_quota_o
output wire int_quota_o,
//MCCU io
output wire int_quota_c0_o,
output wire int_quota_c1_o
);
localparam integer N_COUNTERS = 16;
......@@ -80,7 +85,14 @@
EV1_i,
EV0_i
};
localparam N_CORES = 2;
wire MCCU_int_o [N_CORES-1:0];
//TODO: MCCU_int_o is not assigned parametrically
//A pack array will look better. Consider chang it on the MCCU
// Assign individual signals to unpacked array
assign int_quota_c0_o = MCCU_int_o[0];
assign int_quota_c1_o = MCCU_int_o[1];
// Instantiation of PMU
AXI_PMU_interface_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
......@@ -88,7 +100,9 @@
.N_COUNTERS(N_COUNTERS),
.N_CONF_REGS(N_CONF_REGS),
.OVERFLOW(0), //No
.QUOTA(0) //No
.QUOTA(0), //No
.MCCU(1), //Yes
.N_CORES(2)
) inst_AXI_PMU (
.*
/* .S_AXI_ACLK_i(S_AXI_ACLK_i),
......
......@@ -25,7 +25,7 @@
//Cores. Change this may break Verilator TB
parameter integer N_CORES =4,
//Signals per core. Change this may break Verilator TB
parameter integer CORE_EVENTS =4
parameter integer CORE_EVENTS =4
)
(
input wire clk_i,
......
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Tue Jul 23 13:51:54 2019
[*]
[dumpfile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/MCCU/tb/formal/MCCU/engine_0/trace.vcd"
[dumpfile_mtime] "Tue Jul 23 13:50:06 2019"
[dumpfile_size] 2289
[savefile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/MCCU/tb/formal/MCCU.gtkw"
[timestart] 0
[size] 1920 1025
[pos] 0 27
*-2.734677 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] MCCU.
[sst_width] 326
[signals_width] 262
[sst_expanded] 1
[sst_vpaned_height] 303
@28
[color] 4
MCCU.clk_i
[color] 1
MCCU.enable_i
[color] 1
MCCU.rstn_i
MCCU.interruption_quota_o
@22
[color] 3
MCCU.quota_int<0>[31:0]
@24
[color] 3
MCCU.ccc_suma_int<0>[10:0]
[pattern_trace] 1
[pattern_trace] 0
[options]
mode cover
depth 25
append 2
[engines]
smtbmc
#[script]
#read_verilog -formal MCCU.sv
#prep -top MCCU
#opt -share_all
[script]
verific -vlog-define FORMAL
verific -sv MCCU.sv
verific -import -extnets -all MCCU
prep -top MCCU
[files]
/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/MCCU/hdl/MCCU.sv
$date
Tue Jul 30 13:01:17 2019
$end
$version
QuestaSim Version 10.7c
$end
$timescale
1ps
$end
$scope module tb_MCCU $end
$scope module dut_MCCU $end
$var parameter 32 ! DATA_WIDTH $end
$var parameter 32 " WEIGHTS_WIDTH $end
$var parameter 32 # N_CORES $end
$var parameter 32 $ CORE_EVENTS $end
$var parameter 32 % OVERFLOW_PROT $end
$var parameter 32 & O_D_0PAD $end
$var parameter 32 ' D_W_0PAD $end
$var parameter 32 ( O_W_0PAD $end
$var wire 1 ) clk_i $end
$var wire 1 * rstn_i $end
$var wire 1 + enable_i $end
$var wire 1 , events_i [0] $end
$var wire 1 - quota_i [0] $end
$var wire 1 . quota_i [1] $end
$var wire 1 / quota_i [2] $end
$var wire 1 0 quota_i [3] $end
$var wire 1 1 quota_i [4] $end
$var wire 1 2 quota_i [5] $end
$var wire 1 3 quota_i [6] $end
$var wire 1 4 quota_i [7] $end
$var wire 1 5 quota_i [8] $end
$var wire 1 6 quota_i [9] $end
$var wire 1 7 quota_i [10] $end
$var wire 1 8 quota_i [11] $end
$var wire 1 9 quota_i [12] $end
$var wire 1 : quota_i [13] $end
$var wire 1 ; quota_i [14] $end
$var wire 1 < quota_i [15] $end
$var wire 1 = quota_i [16] $end
$var wire 1 > quota_i [17] $end
$var wire 1 ? quota_i [18] $end
$var wire 1 @ quota_i [19] $end
$var wire 1 A quota_i [20] $end
$var wire 1 B quota_i [21] $end
$var wire 1 C quota_i [22] $end
$var wire 1 D quota_i [23] $end
$var wire 1 E quota_i [24] $end
$var wire 1 F quota_i [25] $end
$var wire 1 G quota_i [26] $end
$var wire 1 H quota_i [27] $end
$var wire 1 I quota_i [28] $end
$var wire 1 J quota_i [29] $end
$var wire 1 K quota_i [30] $end
$var wire 1 L quota_i [31] $end
$var wire 1 M update_quota_i [0] $end
$var wire 1 N quota_o [0] $end
$var wire 1 O quota_o [1] $end
$var wire 1 P quota_o [2] $end
$var wire 1 Q quota_o [3] $end
$var wire 1 R quota_o [4] $end
$var wire 1 S quota_o [5] $end
$var wire 1 T quota_o [6] $end
$var wire 1 U quota_o [7] $end
$var wire 1 V quota_o [8] $end
$var wire 1 W quota_o [9] $end
$var wire 1 X quota_o [10] $end
$var wire 1 Y quota_o [11] $end
$var wire 1 Z quota_o [12] $end
$var wire 1 [ quota_o [13] $end
$var wire 1 \ quota_o [14] $end
$var wire 1 ] quota_o [15] $end
$var wire 1 ^ quota_o [16] $end
$var wire 1 _ quota_o [17] $end
$var wire 1 ` quota_o [18] $end
$var wire 1 a quota_o [19] $end
$var wire 1 b quota_o [20] $end
$var wire 1 c quota_o [21] $end
$var wire 1 d quota_o [22] $end
$var wire 1 e quota_o [23] $end
$var wire 1 f quota_o [24] $end
$var wire 1 g quota_o [25] $end
$var wire 1 h quota_o [26] $end
$var wire 1 i quota_o [27] $end
$var wire 1 j quota_o [28] $end
$var wire 1 k quota_o [29] $end
$var wire 1 l quota_o [30] $end
$var wire 1 m quota_o [31] $end
$var wire 1 n events_weights_i [0] $end
$var wire 1 o events_weights_i [1] $end
$var wire 1 p events_weights_i [2] $end
$var wire 1 q events_weights_i [3] $end
$var wire 1 r events_weights_i [4] $end
$var wire 1 s events_weights_i [5] $end
$var wire 1 t events_weights_i [6] $end
$var wire 1 u interruption_quota_o [0] $end
$var wire 1 v events_weights_int [0] $end
$var wire 1 w events_weights_int [1] $end
$var wire 1 x events_weights_int [2] $end
$var wire 1 y events_weights_int [3] $end
$var wire 1 z events_weights_int [4] $end
$var wire 1 { events_weights_int [5] $end
$var wire 1 | events_weights_int [6] $end
$var integer 32 } i $end
$var integer 32 ~ j $end
$scope begin InterruptionQuota[0] $end
$var parameter 32 !! x $end
$upscope $end
$scope begin SetEventsWeights[0] $end
$var parameter 32 "! x $end
$scope begin genblk1[0] $end
$var parameter 32 #! y $end
$upscope $end
$upscope $end
$scope begin AsyncReset $end
$var reg 64 $! tmp_ccc_suma_int [63:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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