Commit 4e60307f authored by Guillem's avatar Guillem
Browse files

Updated C drivers PMU/MCCU

parent dec3e760
......@@ -92,17 +92,151 @@ uint32_t reset_pmu(void){
var=(uint32_t*)(PMU_BASE+MAIN_CONF_REG);
//var=(uint32_t*)(PMU_BASE+MAIN_CONF_REG);
*var=2;
return *var;
}
uint32_t get_cycles(void){
//reset counters
uint32_t get_overflow_32b(void){
volatile uint32_t *var;
var=(uint32_t*)(PMU_BASE+MAIN_CONF_REG);
//var=(uint32_t*)(PMU_BASE+MAIN_CONF_REG);
*var=2;
for(int i=0; i<N_OVERFLOW_REGS;i++){
var=(uint32_t*)(BASE_OVERFLOW+i*4);
#ifdef __UART__
printf("OVERFLOW REG%d\n",i);
printf("value :%d \n",*var);
#endif
}
return *var;
}
//we write the overflow register to get rid of the interrupt?
uint32_t get_quota_mask_32b(void){
volatile uint32_t *var;
for(int i=0; i<N_QUOTA_MASK;i++){
var=(uint32_t*)(FIRST_QUOTA_MASK+i*4);
#ifdef __UART__
printf("QUOTA MASK REG%d\n",i);
printf("value :%d \n",*var);
#endif
}
return *var;
}
uint32_t set_quota_mask_32b(uint32_t mask[N_QUOTA_MASK]){
volatile uint32_t *var;
for(int i=0; i<N_QUOTA_MASK;i++){
var=(uint32_t*)(FIRST_QUOTA_MASK+i*4);
*var = mask[i];
}
return mask;
}
uint32_t get_quota_limit_32b(void){
volatile uint32_t *var;
for(int i=0; i<N_QUOTA_LIMIT;i++){
var=(uint32_t*)(FIRST_QUOTA_LIMIT+i*4);
#ifdef __UART__
printf("QUOTA_LIMIT REG\n");
printf("value :%d \n",*var);
#endif
}
return *var;
}
uint32_t set_quota_limit_32b(uint32_t limits[N_QUOTA_LIMIT]){
volatile uint32_t *var;
for(int i=0; i<N_QUOTA_LIMIT;i++){
var=(uint32_t*)(FIRST_QUOTA_LIMIT+i*4);
*var = limits[i];
}
return limits;
}
//MCCU functions
uint32_t enable_MCCU_32b(void){
volatile uint32_t *var;
var=(uint32_t*)(BASE_MCCU);
*var = 0x80000000;
return *var;
}
uint32_t update_registers_MCCU_32b(void){
//note that this function disables MCCU. In order to prevent it you can write
//0xffffffff instead
volatile uint32_t *var;
var=(uint32_t*)(BASE_MCCU);
*var = 0x7fffffff;
return *var;
}
uint32_t get_main_config_MCCU_32b(void){
volatile uint32_t *var;
var=(uint32_t*)(BASE_MCCU);
#ifdef __UART__
printf("MCCU main CONFIG REG\n");
printf("value :%d \n",*var);
#endif
return *var;
}
uint32_t get_quota_MCCU_32b(void){
volatile uint32_t *var;
for(int i=0; i<N_CORES_MCCU;i++){
var=(uint32_t*)(FIRST_MCCU_QUOTA+i*4);
#ifdef __UART__
printf("MCCU QUOTA_LIMIT REG\n");
printf("value :%d \n",*var);
#endif
}
}
uint32_t set_quota_MCCU_32b(uint32_t quota[MCCU_N_CORES]){
volatile uint32_t *var;
for(int i=0; i<MCCU_N_CORES;i++){
var=(uint32_t*)(FIRST_MCCU_QUOTA+i*4);
*var = quota[i];
}
return quota;
}
uint32_t get_weights_MCCU_32b(void){
volatile uint32_t *var;
for(int i=0; i<N_REGS_MCCU_WEIGHTS;i++){
var=(uint32_t*)(FIRST_MCCU_WEIGHTS+i*4);
#ifdef __UART__
printf("QUOTA_LIMIT REG\n");
printf("value :%d \n",*var);
#endif
}
}
uint32_t set_weights_MCCU_32b(uint32_t weights[MCCU_WEIGHTS_REGS]){
volatile uint32_t *var;
for(int i=0; i<MCCU_WEIGHTS_REGS;i++){
var=(uint32_t*)(FIRST_MCCU_WEIGHTS+i*4);
*var = weights[i];
}
return weights;
}
//MCCU quota interrupts are not mapped to registers. How do we read them?
uint32_t test_pmu(void){
//call ALL
enable_PMU_32b ();
disable_PMU_32b ();
get_cycles_32b ();
get_instr_32b ();
reset_pmu();
get_overflow_32b();
uint32_t mask [N_QUOTA_MASK] ={0xffff};
set_quota_mask_32b(mask);
get_quota_mask_32b();
uint32_t limits [N_QUOTA_LIMIT] ={0xaaaa};
set_quota_limit_32b(limits);
get_quota_limit_32b();
get_main_config_MCCU_32b();
uint32_t MCCU_quota [MCCU_N_CORES] ={0xcccc,0xdddd};
set_quota_MCCU_32b(MCCU_quota);
get_quota_MCCU_32b();
uint32_t MCCU_weights [MCCU_WEIGHTS_REGS] ={0xbeefbeef,0xcafecafe};
set_weights_MCCU_32b(MCCU_weights);
get_weights_MCCU_32b();
update_registers_MCCU_32b();//note that this function disables MCCU
enable_MCCU_32b();
//enable PMU
read_test_loop(PMU_BASE,PMU_BASE+MASK3,4);
#ifdef __UART__
......@@ -119,6 +253,7 @@ uint32_t test_pmu(void){
printf("\n ***Disable***\n\n");
#endif
disable_PMU_32b ();
get_overflow_32b();
read_test_loop(PMU_BASE,PMU_BASE+MASK3,4);
return(0);
}
......
......@@ -7,6 +7,7 @@
#define PMU_BASE (0x80020000)
#define MASK3 (0x050)
/****** Begin values Specific to each implementation ******/
//TODO: Clean up unused parameters
#define C_S_AXI_DATA_WIDTH 32
#define C_S_AXI_ADDR_WIDTH 7
#define N_COUNTERS 16
......@@ -14,10 +15,11 @@
#define OVERFLOW 1
#define QUOTA 1
#define MCCU 1
#define N_CORES 1
#define N_CORES 2
#define ADDR_LSB 2
#define OPT_MEM_ADDR_BITS 4
#define MAIN_CONF_REG (N_COUNTERS+4)*(C_S_AXI_DATA_WIDTH/8)
#define MAIN_CONF_REG (N_COUNTERS)*(C_S_AXI_DATA_WIDTH/8)
//conditional parameters
#if OVERFLOW
#define N_OVERFLOW_REGS 1 //TODO:parametrize
......@@ -38,7 +40,7 @@
#define MCCU_WEIGHTS_WIDTH 8
#define MCCU_N_CORES N_CORES
#define MCCU_CORE_EVENTS 4
#define MCCU_WEIGHTS_REGS 1 //TODO: parametrize this. More details next line
#define MCCU_WEIGHTS_REGS 2 //TODO: parametrize this. More details next line
//MCCU_WEIGHTS_REGS = 1 (default: ((MCCU==0) ? 0 : (((((MCCU_N_CORES * MCCU_CORE_EVENTS) * MCCU_WEIGHTS_WIDTH) % MCCU_DATA_WIDTH) > 0) ? ((((MCCU_N_CORES * MCCU_CORE_EVENTS) * MCCU_WEIGHTS_WIDTH) / MCCU_DATA_WIDTH) + 1) : (((MCCU_N_CORES * MCCU_CORE_EVENTS) * MCCU_WEIGHTS_WIDTH) / MCCU_DATA_WIDTH))))
#define MCCU_REGS (((1 + MCCU_N_CORES) + MCCU_N_CORES) + MCCU_WEIGHTS_REGS)
#define MCCU_R_REGS MCCU_N_CORES
......@@ -57,11 +59,44 @@
#define MCCU_DATA_WIDTH 0
#endif
#define BASE_QUOTA = ((N_COUNTERS + N_CONF_REGS) + N_OVERFLOW_REGS)
#define BASE_MCCU = ((BASE_QUOTA + N_QUOTA_MASK) + N_QUOTA_LIMIT)
#define R_ONLY_REGS = (N_COUNTERS + MCCU_R_REGS)
#define RW_REGS = (((N_CONF_REGS + N_OVERFLOW_REGS) + N_QUOTA_MASK) + N_QUOTA_LIMIT) + MCCU_RW_REGS)
#define TOTAL_REGS = (R_ONLY_REGS + RW_REGS)
#define BASE_QUOTA ((N_COUNTERS + N_CONF_REGS) + N_OVERFLOW_REGS)
#define BASE_MCCU ((BASE_QUOTA + N_QUOTA_MASK) + N_QUOTA_LIMIT)
#define R_ONLY_REGS (N_COUNTERS + MCCU_R_REGS)
#define RW_REGS ((N_CONF_REGS + N_OVERFLOW_REGS) + N_QUOTA_MASK) + N_QUOTA_LIMIT) + MCCU_RW_REGS)
#define TOTAL_REGS (R_ONLY_REGS + RW_REGS)
//More parameters we may use
//boundaries
#define FIRST_ADDR PMU_BASE
#define N_REGISTERS TOTAL_REGS
#define LAST_ADDR FIRST_ADDR+(N_REGISTERS-1)*4
//Counters addresses
#define BASE_COUNTERS FIRST_ADDR
#define LAST_COUNTER FIRST_ADDR + (N_COUNTERS-1)*4
//cONF_REGS ADDRESSES
#define BASE_CONF LAST_COUNTER + 4
#define LAST_CONF BASE_CONF + (N_CONF_REGS-1)*4
#define MAIN_CONF BASE_CONF
//oVERFLOW REGISTERs
#define N_OVERFLOW N_OVERFLOW_REGS
#define BASE_OVERFLOW LAST_CONF + 4
#define LAST_OVERFLOW BASE_OVERFLOW + (N_OVERFLOW-1)*4
//qUOTA
#define N_QUOTA N_QUOTA_MASK + N_QUOTA_LIMIT
#define BASE_QUOTA LAST_OVERFLOW + 4
#define LAST_QUOTA BASE_QUOTA + (N_QUOTA-1) * 4
#define FIRST_QUOTA_MASK BASE_QUOTA
#define FIRST_QUOTA_LIMIT BASE_QUOTA + (N_QUOTA_MASK)*4
//MCCU
#define N_MCCU MCCU_REGS
#define N_CORES_MCCU MCCU_N_CORES
#define BASE_MCCU LAST_QUOTA + 4
#define LAST_MCCU BASE_MCCU + (N_MCCU-1) *4
#define MAIN_MCCU_CFG BASE_MCCU
#define FIRST_MCCU_QUOTA BASE_MCCU+4
#define FIRST_MCCU_WEIGHTS FIRST_MCCU_QUOTA + (N_CORES_MCCU)*4
#define N_REGS_MCCU_WEIGHTS MCCU_WEIGHTS_REGS
#define FIRST_MCCU_OUT_QUOTA FIRST_MCCU_WEIGHTS + (N_REGS_MCCU_WEIGHTS-1)*4
/****** end values Specific to each implementation ******/
#include <stdio.h>
#ifdef __UART__
......
......@@ -15,7 +15,14 @@ uint32_t bench_pmu(void){
printf("\n ***bench_pmu***\n\n");
#endif
enable_PMU_32b();
// search_loop(IO_BASE,IO_BASE+IO_MASK,4,0xBEAF);
int a=0, b =0;
for(int i = 0 ; i< 0xfffff; i++){
a=i-b;
if(i%3){
b++;
read_test_loop(PMU_BASE,PMU_BASE+MASK3,4);
}
}
disable_PMU_32b ();
read_test_loop(PMU_BASE,PMU_BASE+MASK3,4);
return(0);
......@@ -26,8 +33,8 @@ void main(void){
#endif
// printf("\n ***DELAY***\n\n");
// read_test_loop(PMU_BASE,PMU_BASE+0x01fff,4);
// test_pmu();
bench_pmu();
test_pmu();
//bench_pmu();
//search_loop(IO_BASE,PMU_BASE+IO_MASK,4,0xDEAD);
}
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Mon Sep 16 12:38:15 2019
[*] Wed Sep 18 07:37:13 2019
[*]
[dumpfile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/vsim/write_test.vcd"
[dumpfile_mtime] "Thu Jul 11 09:23:47 2019"
[dumpfile_size] 24338315
[dumpfile_mtime] "Wed Sep 18 07:11:06 2019"
[dumpfile_size] 53953958
[savefile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/tb/verilator/testSOC.gtkw"
[timestart] 15292
[timestart] 4670
[size] 1920 1052
[pos] 0 0
*-7.000000 15730 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-13.000000 20030 16295 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.chip_top.
[treeopen] TOP.chip_top.AXI_PMU_0.
......@@ -30,9 +30,9 @@
[treeopen] TOP.chip_top.Rocket.RocketTile.dcache.dtlb.
[treeopen] TOP.chip_top.Rocket.RocketTile.ptw.
[sst_width] 422
[signals_width] 381
[signals_width] 380
[sst_expanded] 1
[sst_vpaned_height] 345
[sst_vpaned_height] 391
@22
[color] 3
TOP.clk_n
......@@ -253,13 +253,45 @@ TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0]
-group_end
@22
TOP.chip_top.Rocket.RocketTile.core.previous_EXE_PC[39:0]
TOP.chip_top.Rocket.RocketTile.core.previous_EXE_PC[39:0]
TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
@800200
-pmu_regs
@1000200
-pmu_regs
@800200
-PMU_REGS
@28
TOP.chip_top.Rocket.RocketTile.core.EXE_PC_VALID
TOP.chip_top.Rocket.RocketTile.core.new_instruction
[color] 1
TOP.chip_top.new_instruction_c0
[color] 2
TOP.chip_top.clk
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(0)[31:0]
@28
TOP.chip_top.icache_miss_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(1)[31:0]
@28
TOP.chip_top.itlb_miss_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(2)[31:0]
@28
TOP.chip_top.dcache_miss_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(3)[31:0]
@28
[color] 1
+{DTLB_miss} TOP.chip_top.Rocket.RocketTile.dcache.dtlb.tlb_miss
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(4)[31:0]
@28
TOP.chip_top.EXE_STORE_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(5)[31:0]
@28
TOP.chip_top.EXE_LOAD_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(7)[31:0]
@28
[color] 1
TOP.chip_top.new_instruction_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(0)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(1)[31:0]
......@@ -277,14 +309,54 @@ TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(12)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(13)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(14)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(15)[31:0]
@23
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(16)[31:0]
@200
-PMU_main_cfg
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(17)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(18)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(19)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(20)[31:0]
@1000200
-PMU_REGS
@23
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(21)[31:0]
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(22)[31:0]
@200
-PMU_quota_mask
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(23)[31:0]
@200
-PMU_quota_limit
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(24)[31:0]
@200
-MCCU_main_cfg
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(25)[31:0]
@200
-MCCU_quota_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(26)[31:0]
@200
-MCCU_quota_c1
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(27)[31:0]
@200
-MCCU_weights_0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(28)[31:0]
@200
-MCCU_weights_1
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(29)[31:0]
@200
-MCCU_remaining_quota_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(30)[31:0]
@200
-MCCU_remaining_quota_c1
@22
TOP.chip_top.AXI_PMU_0.S_AXI_ARADDR_i[27:0]
TOP.chip_top.AXI_PMU_0.S_AXI_AWADDR_i[27:0]
[pattern_trace] 1
[pattern_trace] 0
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