Commit 4db38610 authored by GuillemCabo's avatar GuillemCabo
Browse files

add quota specs

parent 99f03d5b
\newpage
\section{General purpose of the module}
This module checks the content of the counters selected by the mask register. The value of the selected counters is added and compared against the quota limit register. If the total quota
is exceeded then an interrupt is risen. A single interrupt is generated for this module.\\
\\
To account for a given event a 1 must be set to the Quota mask register. When the mask is 0 the value is not accounted for the quota.\\
\\
The addition of counters is sequential, therefore you could notice up to N cycles (where N is the number of counters) from the point that the quota is exceeded until the point where the interrupt is risen.\\
\\
\section{Design placement}
\label{chapter2}
This modules is meant to be instantiated by the interface agnostic PMU (PMU\_raw.sv). Only one instance of this module is required.
%This module is meant to be a blackbox inside the chisel code. It belongs to the Drac class in the \emph{rocket.scala} file. We can have as many instances of this module as cores are instantiated in the SoC. Currently only single core operation has been tested.
\section{Parameters}
\label{chapter3}
This module requires two integer parameters.REG\_WIDTH and N\_COUNTERS. \\
\textbf{REG\_WIDTH} defines the number of bits that a counter has.\\
\textbf{N\_COUNTERS} defines the amount of counters that are available in the PMU.\\
\\
Given the previous parameters the unit shall generate correct RTL without any manual modification to the source code.\\
\\
A local parameter called max\_width sets the width of the internal adder. max\_width shall guaranty that the addition of all counters will not overflow the internal counter.
%The instance of this module takes no parameters, signal widths are hard-coded to match the SoC.
%Internal parameters and structures such as signals for requests and responses of the caches are imported from drac\_pkg.
\ No newline at end of file
\section{Interface}\label{interface}
\label{chapter 4}
Interface signals of the module are listed in the table below.
%TODO
%\begin{table}[H]
% \centering
% \begin{tabular}{lllll}
% \hline
% Port\_Name & Direction & Width & Index & Description \\
% \hline
% CLK & INPUT & 1 & - & Main clock, up to 200MHz \\
% RST & INPUT & 1 & - & Hard reset. Active LOW \\
% SOFT\_RST & INPUT & 1 & - & Soft reset. Active LOW \\
% RESET\_ADDRESS & INPUT & 40 & - & Inital address of PC after soft or hard reset \\
% CSR\_RW\_RDATA & INPUT & 64 & - & - \\
% \end{tabular}
%\end{table}
\section{Reset behavior}
The module contains two reset signals. One synchronous active high reset enabled by software called softrst\_i, the other is the global reset, called rstn\_i it is asynchronous and active low.\\
\\
Any reset when active shall clear any internal register and set them to 0. Interruptions shall become inactive while the unit is in reset.
\section{What could not happen}
Counter values are registered externally, and they shall not be registered. Addition of registers can be stored internally.\\
\\
Interruptions shall be low while the unit is in reset.\\
\\
The internal adder stores the addition of all counters in suma\_int. Suma\_int shall not overflow even if all counters have the maximum value and they have to be added.\\
\\
\section{Behavior}
\subsection{Counter masking}
Counters are only added to compute towards consumed quota if the corresponding bit is active in the quota\_mask\_i signal. This signals is one-hot encoded, the LSB corresponds to the counter 0 and the MSB to the last counter.\\
\\
The mask bit for each counter is replicated to match the reg\_width. An and mask is applied between the replicated signal and the incomming counter value (counter\_value\_i). The outcome is routed to masked\_counter\_value\_int. If the unit is in reset masked\_counter\_value\_int entries remain 0.\\
\\
\subsection{Sequential addition}
In order to minimize resources a single adder is used and values of counters are added sequentially.\\
\\
Three structures are needed. First we have a \textbf{mask change detection} mechanism, the current mask is stored when the unit is active and compared against the previous value, if the stored mask (old\_mask) is different than the incoming mask (quota\_mask\_i) a one bit signal called new\_mask is set high. The second block is a simple \textbf{control state machine}, if we are in reset or a new mask is detected the state jumps to 0, otherwise the state increase each cycle. When the state machine count (state\_int) reaches the N\_COUNTERS value it is set back to 0. Finally we have the actual\textbf{ sequential addition of counters}, it is stored in suma\_int. If the unit is in reset the addition is set to 0, if a new mask or the state-machine in the second block is 0 the addition is set to 0. Otherwise suma\_int adds its previous value to masked\_counter\_value\_int[n], where n is the value of the state-machine in block two minus one (state\_int-1).
\subsection{Interruption}
The interruption control is simple. It holds the previous state of the interrupt in a register called hold\_intr\_quota. This register is set to 0 at reset, otherwise it applies an or operation between its previous value and the current interrupt output (intr\_quota\_o).\\
\\
The output interrupt (intr\_quota\_o) is high if the sequential addition of counters (suma\_int) is larger than the input quota limit (quota\_limit\_i) or the interrupt was triggered since the last reset (hold\_intr\_quota is high).\\
\\
To clear the interrupt a soft or hard reset shall be performed.\\
\\
\subsection{Packages and structures}
No packages and structures are used in this module.
\section{Special cases, corner cases}
If the quota mask is changed the state-machine that adds the content of the counters shall jump to reset. This will discard the previous addition and start over.\\
\\
The number of N\_COUNTERS shall remain reasonable for each specific implementation of the PMU, large values will increase the latency between the quota been exceeded and the trigger of the interrupt.\\
\\
If the values feed into the unit through counter\_value\_i overflow there is the chance that they overflow after been added to suma\_int. As a result the interrupt of quota may trigger but the values of the counters at that instant may be lower than the limit of quota.
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