Commit 3d06576e authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

add FT MCCU, move TB MCCU & crossbar, update doc, add resource logs

parent 67bc278e
......@@ -12,7 +12,9 @@ rm -f $LOG
# Go to target folder
cd ../tb/questa_sim/ || exit 1
# Declare folders of tests to be executed
declare -a StringArray=("tb_axi_pmu/" "tb_pmu_ahb/" "tb_pmu_raw/" "tb_com_tr/" "tb_hamming16td11/" "tb_hamming32td26/" "tb_reg_sbf/")
declare -a StringArray=("tb_axi_pmu/" "tb_com_tr/" "tb_hamming16td11/" "tb_hamming32td26/"
"tb_pmu_ahb/" "tb_pmu_raw/" "tb_reg_sbf/" "tb_MCCU" "tb_crossbar"
"tb_com_tr/")
# Iterate the string array using for loop
for val in ${StringArray[@]}; do
......
......@@ -81,8 +81,8 @@ Since transients shall occur at the clock's rising edge to allow the counters to
\item \underline{Fail mode:} \textit{quota\_int} is an internal register. It is forwarded to top modules with \textit{quota\_o}. \textit{quota\_int} can suffer permanent faults that are not cleared automatically. This failure mode may result in interrupts not triggering or triggering early. \textbf{Priority High}.\\
\underline{Corrective action:} Replicating the internal register \textit{quota\_int} has a low overhead. Two instances will provide error detection, but tree instances are recommended, allowing for seamless recovery if a failure occurs.\\
\\
\item \underline{Fail mode:}\textit{update\_quota\_i} transient errors can result in incorrect configurations due to unexpected or dropped updates. Misconfiguration affects \textit{quota\_int} and thus the resulting interrupts.\textbf{ Priority high.}\\
\underline{Corrective action:}\\
\item \underline{Fail mode:}\textit{update\_quota\_i} transient errors can result in incorrect configurations due to unexpected or dropped updates. Misconfiguration affects \textit{quota\_int} and thus the resulting interrupts.\textbf{ Low priority.}\\
\underline{Corrective action:} Software can read quota\_o values after each write to ensure no transients have occurred.\\
\\
\item \underline{Fail mode:} \textit{quota\_o} is a wire that takes the value of \textit{quota\_int}. Given that \textit{quota\_int} is protected against permanent upsets, a transient error on the output line may cause incorrect readings for a single cycle.\textit{ Quota\_o} is not used as a control signal and does not affect interrupt generation. \textbf{Priority low}.\\
\underline{Corrective action:} \textit{quota\_o} is signaled to the user-accessible registers to provide more information. Several readings could be performed in quick succession and determine if there was an update. Note that the values will be updated at each cycle if the unit is active. If transients over this signal are a real concern for a particular implementation, hardware error detection is recommended. \\
......
No preview for this file type
......@@ -574,7 +574,7 @@ end
MCCU_enable_int <= regs_i[BASE_MCCU_CFG][0];
end
end
logic MCCU_intr_FT1, MCCU_intr_FT2;
MCCU # (
// Width of data registers
.DATA_WIDTH (REG_WIDTH),
......@@ -582,6 +582,8 @@ end
.WEIGHTS_WIDTH (MCCU_WEIGHTS_WIDTH),
//Cores. Change this may break Verilator TB
.N_CORES (MCCU_N_CORES),
// Fault tolerance mechanisms (FT==0 -> FT disabled)
.FT (FT),
//Signals per core. Change this may break Verilator TB
.CORE_EVENTS (MCCU_N_EVENTS)
)
......@@ -594,6 +596,8 @@ end
.update_quota_i (MCCU_update_quota_int),//Software map
.quota_o (regs_o[BASE_MCCU_QUOTA:END_MCCU_QUOTA]),//write back to a read register
.events_weights_i (MCCU_events_weights_int),//core_events times WEIGHTS_WIDTH registers
.intr_FT1_o (MCCU_intr_FT1),
.intr_FT2_o (MCCU_intr_FT2),
.interruption_quota_o (MCCU_intr_up)//N_CORES output signals Add this to top or single toplevel interrupt and an interrupt vector that identifies the source?
// Individual interrupts allow each core to
// handle their own interrupts , therefore
......@@ -804,13 +808,15 @@ end
// Codestyle. All scopes start with a capital letter
assign intr_FT1_o = |{
Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1,
Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1
Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1,
MCCU_intr_FT1
};
//Gather all the signals of uncorrected errors from FT scopes
// Codestyle. All scopes start with a capital letter
assign intr_FT2_o = |{
Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2,
Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2
Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2,
MCCU_intr_FT2
};
end
/////////////////////////////////////////////////////////////////////////////////
......
......@@ -26,6 +26,8 @@
parameter integer WEIGHTS_WIDTH = 8,
//Cores. Change this may break Verilator TB
parameter integer N_CORES =2,
// Fault tolerance mechanisms (FT==0 -> FT disabled)
parameter integer FT = 1,
//Signals per core. Change this may break Verilator TB
parameter integer CORE_EVENTS =4
)
......@@ -49,7 +51,11 @@
input wire [WEIGHTS_WIDTH-1:0] events_weights_i [0:N_CORES-1]
[0:CORE_EVENTS-1],
//Quota interruption
output wire interruption_quota_o[N_CORES-1:0]
output wire interruption_quota_o[N_CORES-1:0],
// FT (Fault tolerance) interrupt, error detected and recovered
output wire intr_FT1_o,
// FT (Fault tolerance) interrupt, error detected but not recoverable
output wire intr_FT2_o
);
//Parameters required for additions and substractions of quotas.
//OVERFLOW_PROT can be reduced. It needs to be a bit larger than
......@@ -63,10 +69,7 @@
localparam O_W_0PAD = OVERFLOW_PROT-WEIGHTS_WIDTH;
//internal signals
reg [DATA_WIDTH-1:0] quota_int [0:N_CORES-1];//Quota set by external registers
wire [WEIGHTS_WIDTH-1:0] events_weights_int [0:N_CORES-1] [0:CORE_EVENTS-1];
reg [OVERFLOW_PROT-1:0] ccc_suma_int [0:N_CORES-1];//Addition of current cycle
//consumed quota
`ifdef DEBUG
reg [OVERFLOW_PROT-1:0] debug_ccc_suma_int;//Just one core
reg [OVERFLOW_PROT-1:0] debug_ccc_suma_loop_int;//Just one core
......@@ -78,9 +81,14 @@
Generate one mechanism to monitor the quota for each of the cores in the
SOC,
----------*/
if (FT==0) begin : Nft_suma
// Define internal signals within generate scope
reg [OVERFLOW_PROT-1:0] ccc_suma_int [0:N_CORES-1];//Addition of current cycle
//consumed quota
reg [DATA_WIDTH-1:0] quota_int [0:N_CORES-1];//Quota set by external registers
integer i;
integer j;
// generate begin : GeneratedQuotaMonitor
// generate begin : GeneratedQuotaMonitor
always @(posedge clk_i) begin: syncReset
/*----------
Auxiliar variables
......@@ -245,6 +253,179 @@
end
end
end
end else begin : Ft_suma
// Code for FT version
//Triplicate registers of interest
//Addition of current cycle consumed quota
reg [OVERFLOW_PROT-1:0] ccc_suma_int_0 [0:N_CORES-1];
reg [OVERFLOW_PROT-1:0] ccc_suma_int_1 [0:N_CORES-1];
reg [OVERFLOW_PROT-1:0] ccc_suma_int_2 [0:N_CORES-1];
//Voted ccc_suma_int
logic [OVERFLOW_PROT-1:0] ccc_suma_vint [0:N_CORES-1];
logic interruption_ccc_suma_fte1, interruption_ccc_suma_fte2;
//Quota set by external registers
reg [DATA_WIDTH-1:0] quota_int_0 [0:N_CORES-1];
reg [DATA_WIDTH-1:0] quota_int_1 [0:N_CORES-1];
reg [DATA_WIDTH-1:0] quota_int_2 [0:N_CORES-1];
//Voted quota int
logic [DATA_WIDTH-1:0] quota_vint [0:N_CORES-1];
logic interruption_quota_fte1, interruption_quota_fte2;
// generate loop vars
integer i;
integer j;
//Generate voted outputs
way3ua_voter #(
.W(OVERFLOW_PROT),
.U(N_CORES)
)ccc_sum_way3(
.in0(ccc_suma_int_0),
.in1(ccc_suma_int_1),
.in2(ccc_suma_int_2),
.out(ccc_suma_vint),
.error1_o(interruption_ccc_suma_fte1),
.error2_o(interruption_ccc_suma_fte2)
);
way3ua_voter #(
.W(DATA_WIDTH),
.U(N_CORES)
)quota_way3(
.in0(quota_int_0),
.in1(quota_int_1),
.in2(quota_int_2),
.out(quota_vint),
.error1_o(interruption_quota_fte1),
.error2_o(interruption_quota_fte2)
);
// generate begin : GeneratedQuotaMonitor
always @(posedge clk_i) begin: syncReset
/*----------
Auxiliar variables
----------*/
longint tmp_ccc_suma_int;//temporal addition of ccc_suma_int
/*----------
Reset
----------*/
if(rstn_i == 1'b0 ) begin
/*----------
sync reset Quota
----------*/
for (i=0; i<N_CORES; i=i+1) begin : ResetQuota
quota_int_0[i] <={DATA_WIDTH{1'b0}};
quota_int_1[i] <={DATA_WIDTH{1'b0}};
quota_int_2[i] <={DATA_WIDTH{1'b0}};
end
/*----------
sync reset current cycle consumed quota
----------*/
for (i=0; i<N_CORES; i=i+1) begin : ResetCCCQuota
ccc_suma_int_0[i] <={OVERFLOW_PROT{1'b0}};
ccc_suma_int_1[i] <={OVERFLOW_PROT{1'b0}};
ccc_suma_int_2[i] <={OVERFLOW_PROT{1'b0}};
end
end else begin
/*----------
Normal operation
----------*/
/*----------
Substract to the core quota the weight of each active
event during this cycle. If the event is active the value
of the weight is substracted, if not 0 is substracted. Only
substract quota if enable is active. If the quota has been updated
this cycle quota_i is bypass
----------*/
for (i=0; i<N_CORES; i=i+1) begin : SetQuota
//!Enable && !update: hold values quota_int
if(!enable_i && !update_quota_i[i]) begin
quota_int_0[i] <= quota_vint[i];
quota_int_1[i] <= quota_vint[i];
quota_int_2[i] <= quota_vint[i];
//!Enable && update: Update values quota_int with quota_i,
// do NOT substract
end else if (!enable_i && update_quota_i[i]) begin
quota_int_0[i] <= quota_i[i];
quota_int_1[i] <= quota_i[i];
quota_int_2[i] <= quota_i[i];
//Enable && !update:Replace quota_int with quota_int minus
// consumed quota (ccc_quota)
end else if (enable_i && !update_quota_i[i]) begin
for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for
// prevent width mismatch
if( ccc_suma_vint[i] > {{O_D_0PAD{1'b0}},quota_vint[i]} )
begin
quota_int_0[i] <={DATA_WIDTH{1'b0}};
quota_int_1[i] <={DATA_WIDTH{1'b0}};
quota_int_2[i] <={DATA_WIDTH{1'b0}};
end else begin
quota_int_0[i] <= quota_vint[i] - ccc_suma_vint[i][DATA_WIDTH-1:0];
quota_int_1[i] <= quota_vint[i] - ccc_suma_vint[i][DATA_WIDTH-1:0];
quota_int_2[i] <= quota_vint[i] - ccc_suma_vint[i][DATA_WIDTH-1:0];
end
end
//Enable && update: Update values quota_int with quota_i and
// substract ccc_quota
end else if(enable_i && update_quota_i[i])begin
for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for
// prevent width mismatch
if( ccc_suma_vint[i] > {{O_D_0PAD{1'b0}},quota_i[i]} )
begin
quota_int_0[i] <={DATA_WIDTH{1'b0}};
quota_int_1[i] <={DATA_WIDTH{1'b0}};
quota_int_2[i] <={DATA_WIDTH{1'b0}};
end else begin
quota_int_0[i] <= quota_i[i] - ccc_suma_vint[i][DATA_WIDTH-1:0];
quota_int_1[i] <= quota_i[i] - ccc_suma_vint[i][DATA_WIDTH-1:0];
quota_int_2[i] <= quota_i[i] - ccc_suma_vint[i][DATA_WIDTH-1:0];
end
end
end
end
/*----------
Add quotas of all active signals. The ones that are not
enabled are 0. The quotas in ccc_suma_int[i] are added at every
cycle independently of the enable signal, but ccc_suma_int will
only be substracted to the quota if MCCU is enabled
----------*/
for (i=0; i<N_CORES; i=i+1) begin : AddEventsWeights
tmp_ccc_suma_int=0;
for (j=0; j<CORE_EVENTS; j=j+1) begin
//Reguired to avoid warning. Blocking
//Assigment is legal when usign temporal
//variables.
/* verilator lint_off BLKSEQ */
tmp_ccc_suma_int ={{O_W_0PAD{1'b0}},events_weights_int[i][j]} + tmp_ccc_suma_int;
/* verilator lint_on BLKSEQ */
end
ccc_suma_int_0[i]<=tmp_ccc_suma_int;
ccc_suma_int_1[i]<=tmp_ccc_suma_int;
ccc_suma_int_2[i]<=tmp_ccc_suma_int;
`ifdef DEBUG
/* verilator lint_off WIDTH */
/* verilator lint_off BLKSEQ */
//This only applies when 4 events are available
if(i==0 && CORE_EVENTS==4) begin
debug_events_weights_int <= events_weights_int [0];//assign to core 0
debug_ccc_suma_int <= debug_events_weights_int[0]+debug_events_weights_int[1]+debug_events_weights_int[2]+debug_events_weights_int[3];
debug_tmp=0;
for(k=0; k<CORE_EVENTS; k=k+1) begin
debug_tmp =debug_events_weights_int[k] + debug_tmp;
end
debug_ccc_suma_loop_int <= debug_tmp;
end
`ifdef ASSERTIONS
assert(debug_ccc_suma_int == debug_ccc_suma_loop_int);
`endif
//disable BLKSeK for the temporal assigment of debug_tmp
/* verilator lint_on BLKSEQ */
/* verilator lint_on WIDTH */
`endif
end
end
end
end
/*----------
Set weights of events, as this module is used whith a
wrapper the values are already registered
......@@ -268,12 +449,21 @@
wire interruption_quota_d[N_CORES-1:0];
reg interruption_quota_q[N_CORES-1:0];
if (FT==0) begin
for(x=0; x<N_CORES; x=x+1) begin: InterruptionQuota
assign interruption_quota_d[x] =
!enable_i ? 1'b0:
(ccc_suma_int[x]>{{O_D_0PAD{1'b0}},quota_int[x]})? 1'b1:1'b0;
(Nft_suma.ccc_suma_int[x]>{{O_D_0PAD{1'b0}},Nft_suma.quota_int[x]})? 1'b1:1'b0;
end
end else begin
for(x=0; x<N_CORES; x=x+1) begin: InterruptionQuota
assign interruption_quota_d[x] =
!enable_i ? 1'b0:
(Ft_suma.ccc_suma_vint[x]>{{O_D_0PAD{1'b0}},Ft_suma.quota_vint[x]})? 1'b1:1'b0;
end
end
for(x=0; x<N_CORES; x=x+1) begin: InterruptionQuotaHold
always @(posedge clk_i) begin
if(rstn_i == 1'b0 ) begin
......@@ -300,8 +490,32 @@
/*----------
forward results of internal registers
----------*/
assign quota_o = quota_int;
if (FT==0) begin
assign quota_o = Nft_suma.quota_int;
end else begin
assign quota_o = Ft_suma.quota_vint;
end
//----------------------------------------------
//------------- Generate intr_FT_o
//----------------------------------------------
if (FT == 0 ) begin
assign intr_FT1_o = 1'b0;
assign intr_FT2_o = 1'b0;
end else begin
//Gather all the signals of corrected errors from FT scopes
// Codestyle. All scopes start with a capital letter
assign intr_FT1_o = |{
Ft_suma.interruption_ccc_suma_fte1,
Ft_suma.interruption_quota_fte1
};
//Gather all the signals of uncorrected errors from FT scopes
// Codestyle. All scopes start with a capital letter
assign intr_FT2_o = |{
Ft_suma.interruption_ccc_suma_fte2,
Ft_suma.interruption_quota_fte2
};
end
/*----------
Section of Formal propperties, valid for SBY
----------*/
......
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......@@ -28,15 +28,15 @@ VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'instances.sv'
3. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'triple_reg.sv'
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/triple_reg.sv'
4. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'sbf_reg.sv'
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/sbf_reg.sv'
5. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'ham_reg.sv'
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/ham_reg.sv'
6. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
......@@ -64,11 +64,11 @@ Adding Verilog module 'instances' to elaboration queue.
Running hier_tree::Elaborate().
VERIFIC-INFO [VERI-1018] instances.sv:20: compiling module 'instances'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/com_tr.sv:21: compiling module 'com_tr(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] triple_reg.sv:16: compiling module 'triple_reg(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/triple_reg.sv:16: compiling module 'triple_reg(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/way3_voter.sv:24: compiling module 'way3_voter'
VERIFIC-INFO [VERI-1018] sbf_reg.sv:16: compiling module 'sbf_reg(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/sbf_reg.sv:16: compiling module 'sbf_reg(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/reg_sbf.sv:26: compiling module 'reg_sbf'
VERIFIC-INFO [VERI-1018] ham_reg.sv:16: compiling module 'ham_reg'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/ham_reg.sv:16: compiling module 'ham_reg'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_enc.sv:18: compiling module 'hamming16t11d_enc'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_dec.sv:18: compiling module 'hamming16t11d_dec'
Importing module instances.
......@@ -139,7 +139,6 @@ Optimizing module way3_voter.
Optimizing module sbf_reg(IN_WIDTH=32).
Optimizing module ham_reg.
Optimizing module triple_reg(IN_WIDTH=32).
<suppressed ~2 debug messages>
Optimizing module com_tr(IN_WIDTH=32).
Optimizing module instances.
......@@ -153,8 +152,8 @@ Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \com_tr(IN_WIDTH=32)..
Finding unused cells or wires in module \instances..
Removed 2 unused cells and 429 unused wires.
<suppressed ~23 debug messages>
Removed 1 unused cells and 427 unused wires.
<suppressed ~22 debug messages>
12.5. Executing CHECK pass (checking for obvious problems).
checking module com_tr(IN_WIDTH=32)..
......@@ -190,9 +189,9 @@ Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf'.
Finding identical cells in module `\sbf_reg(IN_WIDTH=32)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=32)'.
<suppressed ~3 debug messages>
<suppressed ~6 debug messages>
Finding identical cells in module `\way3_voter'.
Removed a total of 1 cells.
Removed a total of 2 cells.
12.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=32)..
......@@ -230,11 +229,11 @@ Running muxtree optimizer on module \way3_voter..
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>
<suppressed ~20 debug messages>
12.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32).
New input vector for $reduce_or cell $verific$reduce_or_12$../../submodules/seu_ip/com_tr.sv:62$174: { $verific$n140$168 [0] $verific$n140$168 [1] $verific$n140$168 [2] $verific$n140$168 [3] $verific$n140$168 [4] $verific$n140$168 [5] $verific$n140$168 [6] $verific$n140$168 [7] $verific$n140$168 [8] $verific$n140$168 [9] $verific$n140$168 [10] $verific$n140$168 [11] $verific$n140$168 [12] $verific$n140$168 [13] $verific$n140$168 [14] $verific$n140$168 [15] $verific$n140$168 [16] $verific$n140$168 [17] $verific$n140$168 [18] $verific$n140$168 [19] $verific$n140$168 [20] $verific$n140$168 [21] $verific$n140$168 [22] $verific$n140$168 [23] $verific$n140$168 [24] $verific$n140$168 [25] $verific$n140$168 [26] $verific$n140$168 [27] $verific$n140$168 [28] $verific$n140$168 [29] $verific$n140$168 [30] $verific$n140$168 [31] }
New input vector for $reduce_or cell $verific$reduce_or_12$../../submodules/seu_ip/com_tr.sv:62$173: { $verific$n140$167 [0] $verific$n140$167 [1] $verific$n140$167 [2] $verific$n140$167 [3] $verific$n140$167 [4] $verific$n140$167 [5] $verific$n140$167 [6] $verific$n140$167 [7] $verific$n140$167 [8] $verific$n140$167 [9] $verific$n140$167 [10] $verific$n140$167 [11] $verific$n140$167 [12] $verific$n140$167 [13] $verific$n140$167 [14] $verific$n140$167 [15] $verific$n140$167 [16] $verific$n140$167 [17] $verific$n140$167 [18] $verific$n140$167 [19] $verific$n140$167 [20] $verific$n140$167 [21] $verific$n140$167 [22] $verific$n140$167 [23] $verific$n140$167 [24] $verific$n140$167 [25] $verific$n140$167 [26] $verific$n140$167 [27] $verific$n140$167 [28] $verific$n140$167 [29] $verific$n140$167 [30] $verific$n140$167 [31] }
Optimizing cells in module \com_tr(IN_WIDTH=32).
Optimizing cells in module \ham_reg.
Optimizing cells in module \hamming16t11d_dec.
......@@ -320,7 +319,7 @@ Running muxtree optimizer on module \way3_voter..
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>
<suppressed ~20 debug messages>
12.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32).
......@@ -373,10 +372,10 @@ Optimizing module way3_voter.
12.6.16. Finished OPT passes. (There is nothing left to do.)
12.7. Executing WREDUCE pass (reducing word size of cells).
Removed top 2 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_11$../../submodules/seu_ip/hamming16t11d_dec.sv:75$541 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_14$../../submodules/seu_ip/hamming16t11d_dec.sv:76$544 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_17$../../submodules/seu_ip/hamming16t11d_dec.sv:77$547 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_20$../../submodules/seu_ip/hamming16t11d_dec.sv:78$550 ($eq).
Removed top 2 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_11$../../submodules/seu_ip/hamming16t11d_dec.sv:45$536 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_14$../../submodules/seu_ip/hamming16t11d_dec.sv:46$539 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_17$../../submodules/seu_ip/hamming16t11d_dec.sv:47$542 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_20$../../submodules/seu_ip/hamming16t11d_dec.sv:48$545 ($eq).
12.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
......@@ -526,10 +525,10 @@ Finding unused cells or wires in module \way3_voter..
=== sbf_reg(IN_WIDTH=32) ===
Number of wires: 10
Number of wire bits: 165
Number of public wires: 9
Number of public wire bits: 133
Number of wires: 9
Number of wire bits: 164
Number of public wires: 8
Number of public wire bits: 132
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
......@@ -540,16 +539,16 @@ Finding unused cells or wires in module \way3_voter..
=== triple_reg(IN_WIDTH=32) ===
Number of wires: 18
Number of wire bits: 390
Number of wires: 17
Number of wire bits: 358
Number of public wires: 16
Number of public wire bits: 326
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 5
$dff 2
$mux 2
Number of cells: 3
$dff 1
$mux 1
way3_voter 1
=== way3_voter ===
......@@ -579,18 +578,18 @@ Finding unused cells or wires in module \way3_voter..
triple_reg(IN_WIDTH=32) 1
way3_voter 1
Number of wires: 117
Number of wire bits: 1265
Number of public wires: 76
Number of public wire bits: 992
Number of wires: 115
Number of wire bits: 1232
Number of public wires: 75
Number of public wire bits: 991
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 77
Number of cells: 75
$and 1
$dff 8
$dff 7
$eq 14
$mux 24
$mux 23
$ne 1
$not 13
$reduce_bool 1
......@@ -692,7 +691,7 @@ Running muxtree optimizer on module \way3_voter..
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>
<suppressed ~20 debug messages>
14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32).
......@@ -719,8 +718,6 @@ Finding identical cells in module `\way3_voter'.
Removed a total of 0 cells.
14.6. Executing OPT_RMDFF pass (remove dff with constant values).
Removing $verific$trip2_preg_reg$triple_reg.sv:62$189 ($dff) from module triple_reg(IN_WIDTH=32).
Replaced 1 DFF cells.
14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=32)..
......@@ -732,8 +729,6 @@ Finding unused cells or wires in module \reg_sbf..
Finding unused cells or wires in module \sbf_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \way3_voter..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>
14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=32).
......@@ -746,95 +741,7 @@ Optimizing module sbf_reg(IN_WIDTH=32).
Optimizing module triple_reg(IN_WIDTH=32).
Optimizing module way3_voter.
14.9. Rerunning OPT passes. (Maybe there is more to do..)
14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=32)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \instances..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \reg_sbf..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \sbf_reg(IN_WIDTH=32)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=32)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~20 debug messages>
14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32).
Optimizing cells in module \ham_reg.
Optimizing cells in module \hamming16t11d_dec.
Optimizing cells in module \hamming16t11d_enc.
Optimizing cells in module \instances.
Optimizing cells in module \reg_sbf.
Optimizing cells in module \sbf_reg(IN_WIDTH=32).
Optimizing cells in module \triple_reg(IN_WIDTH=32).
Optimizing cells in module \way3_voter.
Performed a total of 0 changes.
14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=32)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf'.
Finding identical cells in module `\sbf_reg(IN_WIDTH=32)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=32)'.
Finding identical cells in module `\way3_voter'.
Removed a total of 0 cells.
14.13. Executing OPT_RMDFF pass (remove dff with constant values).
14.14. Executing OPT_CLEAN pass (remove unused cells and wires).