Commit 3d06576e authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

add FT MCCU, move TB MCCU & crossbar, update doc, add resource logs

parent 67bc278e
...@@ -12,7 +12,9 @@ rm -f $LOG ...@@ -12,7 +12,9 @@ rm -f $LOG
# Go to target folder # Go to target folder
cd ../tb/questa_sim/ || exit 1 cd ../tb/questa_sim/ || exit 1
# Declare folders of tests to be executed # Declare folders of tests to be executed
declare -a StringArray=("tb_axi_pmu/" "tb_pmu_ahb/" "tb_pmu_raw/" "tb_com_tr/" "tb_hamming16td11/" "tb_hamming32td26/" "tb_reg_sbf/") declare -a StringArray=("tb_axi_pmu/" "tb_com_tr/" "tb_hamming16td11/" "tb_hamming32td26/"
"tb_pmu_ahb/" "tb_pmu_raw/" "tb_reg_sbf/" "tb_MCCU" "tb_crossbar"
"tb_com_tr/")
# Iterate the string array using for loop # Iterate the string array using for loop
for val in ${StringArray[@]}; do for val in ${StringArray[@]}; do
......
...@@ -81,8 +81,8 @@ Since transients shall occur at the clock's rising edge to allow the counters to ...@@ -81,8 +81,8 @@ Since transients shall occur at the clock's rising edge to allow the counters to
\item \underline{Fail mode:} \textit{quota\_int} is an internal register. It is forwarded to top modules with \textit{quota\_o}. \textit{quota\_int} can suffer permanent faults that are not cleared automatically. This failure mode may result in interrupts not triggering or triggering early. \textbf{Priority High}.\\ \item \underline{Fail mode:} \textit{quota\_int} is an internal register. It is forwarded to top modules with \textit{quota\_o}. \textit{quota\_int} can suffer permanent faults that are not cleared automatically. This failure mode may result in interrupts not triggering or triggering early. \textbf{Priority High}.\\
\underline{Corrective action:} Replicating the internal register \textit{quota\_int} has a low overhead. Two instances will provide error detection, but tree instances are recommended, allowing for seamless recovery if a failure occurs.\\ \underline{Corrective action:} Replicating the internal register \textit{quota\_int} has a low overhead. Two instances will provide error detection, but tree instances are recommended, allowing for seamless recovery if a failure occurs.\\
\\ \\
\item \underline{Fail mode:}\textit{update\_quota\_i} transient errors can result in incorrect configurations due to unexpected or dropped updates. Misconfiguration affects \textit{quota\_int} and thus the resulting interrupts.\textbf{ Priority high.}\\ \item \underline{Fail mode:}\textit{update\_quota\_i} transient errors can result in incorrect configurations due to unexpected or dropped updates. Misconfiguration affects \textit{quota\_int} and thus the resulting interrupts.\textbf{ Low priority.}\\
\underline{Corrective action:}\\ \underline{Corrective action:} Software can read quota\_o values after each write to ensure no transients have occurred.\\
\\ \\
\item \underline{Fail mode:} \textit{quota\_o} is a wire that takes the value of \textit{quota\_int}. Given that \textit{quota\_int} is protected against permanent upsets, a transient error on the output line may cause incorrect readings for a single cycle.\textit{ Quota\_o} is not used as a control signal and does not affect interrupt generation. \textbf{Priority low}.\\ \item \underline{Fail mode:} \textit{quota\_o} is a wire that takes the value of \textit{quota\_int}. Given that \textit{quota\_int} is protected against permanent upsets, a transient error on the output line may cause incorrect readings for a single cycle.\textit{ Quota\_o} is not used as a control signal and does not affect interrupt generation. \textbf{Priority low}.\\
\underline{Corrective action:} \textit{quota\_o} is signaled to the user-accessible registers to provide more information. Several readings could be performed in quick succession and determine if there was an update. Note that the values will be updated at each cycle if the unit is active. If transients over this signal are a real concern for a particular implementation, hardware error detection is recommended. \\ \underline{Corrective action:} \textit{quota\_o} is signaled to the user-accessible registers to provide more information. Several readings could be performed in quick succession and determine if there was an update. Note that the values will be updated at each cycle if the unit is active. If transients over this signal are a real concern for a particular implementation, hardware error detection is recommended. \\
......
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...@@ -574,7 +574,7 @@ end ...@@ -574,7 +574,7 @@ end
MCCU_enable_int <= regs_i[BASE_MCCU_CFG][0]; MCCU_enable_int <= regs_i[BASE_MCCU_CFG][0];
end end
end end
logic MCCU_intr_FT1, MCCU_intr_FT2;
MCCU # ( MCCU # (
// Width of data registers // Width of data registers
.DATA_WIDTH (REG_WIDTH), .DATA_WIDTH (REG_WIDTH),
...@@ -582,6 +582,8 @@ end ...@@ -582,6 +582,8 @@ end
.WEIGHTS_WIDTH (MCCU_WEIGHTS_WIDTH), .WEIGHTS_WIDTH (MCCU_WEIGHTS_WIDTH),
//Cores. Change this may break Verilator TB //Cores. Change this may break Verilator TB
.N_CORES (MCCU_N_CORES), .N_CORES (MCCU_N_CORES),
// Fault tolerance mechanisms (FT==0 -> FT disabled)
.FT (FT),
//Signals per core. Change this may break Verilator TB //Signals per core. Change this may break Verilator TB
.CORE_EVENTS (MCCU_N_EVENTS) .CORE_EVENTS (MCCU_N_EVENTS)
) )
...@@ -594,6 +596,8 @@ end ...@@ -594,6 +596,8 @@ end
.update_quota_i (MCCU_update_quota_int),//Software map .update_quota_i (MCCU_update_quota_int),//Software map
.quota_o (regs_o[BASE_MCCU_QUOTA:END_MCCU_QUOTA]),//write back to a read register .quota_o (regs_o[BASE_MCCU_QUOTA:END_MCCU_QUOTA]),//write back to a read register
.events_weights_i (MCCU_events_weights_int),//core_events times WEIGHTS_WIDTH registers .events_weights_i (MCCU_events_weights_int),//core_events times WEIGHTS_WIDTH registers
.intr_FT1_o (MCCU_intr_FT1),
.intr_FT2_o (MCCU_intr_FT2),
.interruption_quota_o (MCCU_intr_up)//N_CORES output signals Add this to top or single toplevel interrupt and an interrupt vector that identifies the source? .interruption_quota_o (MCCU_intr_up)//N_CORES output signals Add this to top or single toplevel interrupt and an interrupt vector that identifies the source?
// Individual interrupts allow each core to // Individual interrupts allow each core to
// handle their own interrupts , therefore // handle their own interrupts , therefore
...@@ -804,13 +808,15 @@ end ...@@ -804,13 +808,15 @@ end
// Codestyle. All scopes start with a capital letter // Codestyle. All scopes start with a capital letter
assign intr_FT1_o = |{ assign intr_FT1_o = |{
Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1, Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1,
Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1 Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1,
MCCU_intr_FT1
}; };
//Gather all the signals of uncorrected errors from FT scopes //Gather all the signals of uncorrected errors from FT scopes
// Codestyle. All scopes start with a capital letter // Codestyle. All scopes start with a capital letter
assign intr_FT2_o = |{ assign intr_FT2_o = |{
Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2, Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2,
Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2 Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2,
MCCU_intr_FT2
}; };
end end
///////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////
......
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...@@ -28,15 +28,15 @@ VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'instances.sv' ...@@ -28,15 +28,15 @@ VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'instances.sv'
3. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific). 3. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019. Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'triple_reg.sv' VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/triple_reg.sv'
4. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific). 4. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019. Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'sbf_reg.sv' VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/sbf_reg.sv'
5. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific). 5. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019. Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'ham_reg.sv' VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/ham_reg.sv'
6. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific). 6. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019. Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
...@@ -64,11 +64,11 @@ Adding Verilog module 'instances' to elaboration queue. ...@@ -64,11 +64,11 @@ Adding Verilog module 'instances' to elaboration queue.
Running hier_tree::Elaborate(). Running hier_tree::Elaborate().
VERIFIC-INFO [VERI-1018] instances.sv:20: compiling module 'instances' VERIFIC-INFO [VERI-1018] instances.sv:20: compiling module 'instances'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/com_tr.sv:21: compiling module 'com_tr(IN_WIDTH=32)' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/com_tr.sv:21: compiling module 'com_tr(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] triple_reg.sv:16: compiling module 'triple_reg(IN_WIDTH=32)' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/triple_reg.sv:16: compiling module 'triple_reg(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/way3_voter.sv:24: compiling module 'way3_voter' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/way3_voter.sv:24: compiling module 'way3_voter'
VERIFIC-INFO [VERI-1018] sbf_reg.sv:16: compiling module 'sbf_reg(IN_WIDTH=32)' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/sbf_reg.sv:16: compiling module 'sbf_reg(IN_WIDTH=32)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/reg_sbf.sv:26: compiling module 'reg_sbf' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/reg_sbf.sv:26: compiling module 'reg_sbf'
VERIFIC-INFO [VERI-1018] ham_reg.sv:16: compiling module 'ham_reg' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/ham_reg.sv:16: compiling module 'ham_reg'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_enc.sv:18: compiling module 'hamming16t11d_enc' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_enc.sv:18: compiling module 'hamming16t11d_enc'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_dec.sv:18: compiling module 'hamming16t11d_dec' VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_dec.sv:18: compiling module 'hamming16t11d_dec'
Importing module instances. Importing module instances.
...@@ -139,7 +139,6 @@ Optimizing module way3_voter. ...@@ -139,7 +139,6 @@ Optimizing module way3_voter.
Optimizing module sbf_reg(IN_WIDTH=32). Optimizing module sbf_reg(IN_WIDTH=32).
Optimizing module ham_reg. Optimizing module ham_reg.
Optimizing module triple_reg(IN_WIDTH=32). Optimizing module triple_reg(IN_WIDTH=32).
<suppressed ~2 debug messages>
Optimizing module com_tr(IN_WIDTH=32). Optimizing module com_tr(IN_WIDTH=32).
Optimizing module instances. Optimizing module instances.
...@@ -153,8 +152,8 @@ Finding unused cells or wires in module \ham_reg.. ...@@ -153,8 +152,8 @@ Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=32).. Finding unused cells or wires in module \triple_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \com_tr(IN_WIDTH=32).. Finding unused cells or wires in module \com_tr(IN_WIDTH=32)..
Finding unused cells or wires in module \instances.. Finding unused cells or wires in module \instances..
Removed 2 unused cells and 429 unused wires. Removed 1 unused cells and 427 unused wires.
<suppressed ~23 debug messages> <suppressed ~22 debug messages>
12.5. Executing CHECK pass (checking for obvious problems). 12.5. Executing CHECK pass (checking for obvious problems).
checking module com_tr(IN_WIDTH=32).. checking module com_tr(IN_WIDTH=32)..
...@@ -190,9 +189,9 @@ Finding identical cells in module `\instances'. ...@@ -190,9 +189,9 @@ Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf'. Finding identical cells in module `\reg_sbf'.
Finding identical cells in module `\sbf_reg(IN_WIDTH=32)'. Finding identical cells in module `\sbf_reg(IN_WIDTH=32)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=32)'. Finding identical cells in module `\triple_reg(IN_WIDTH=32)'.
<suppressed ~3 debug messages> <suppressed ~6 debug messages>
Finding identical cells in module `\way3_voter'. Finding identical cells in module `\way3_voter'.
Removed a total of 1 cells. Removed a total of 2 cells.
12.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 12.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=32).. Running muxtree optimizer on module \com_tr(IN_WIDTH=32)..
...@@ -230,11 +229,11 @@ Running muxtree optimizer on module \way3_voter.. ...@@ -230,11 +229,11 @@ Running muxtree optimizer on module \way3_voter..
Evaluating internal representation of mux trees. Evaluating internal representation of mux trees.
Analyzing evaluation results. Analyzing evaluation results.
Removed 0 multiplexer ports. Removed 0 multiplexer ports.
<suppressed ~21 debug messages> <suppressed ~20 debug messages>
12.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 12.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32). Optimizing cells in module \com_tr(IN_WIDTH=32).
New input vector for $reduce_or cell $verific$reduce_or_12$../../submodules/seu_ip/com_tr.sv:62$174: { $verific$n140$168 [0] $verific$n140$168 [1] $verific$n140$168 [2] $verific$n140$168 [3] $verific$n140$168 [4] $verific$n140$168 [5] $verific$n140$168 [6] $verific$n140$168 [7] $verific$n140$168 [8] $verific$n140$168 [9] $verific$n140$168 [10] $verific$n140$168 [11] $verific$n140$168 [12] $verific$n140$168 [13] $verific$n140$168 [14] $verific$n140$168 [15] $verific$n140$168 [16] $verific$n140$168 [17] $verific$n140$168 [18] $verific$n140$168 [19] $verific$n140$168 [20] $verific$n140$168 [21] $verific$n140$168 [22] $verific$n140$168 [23] $verific$n140$168 [24] $verific$n140$168 [25] $verific$n140$168 [26] $verific$n140$168 [27] $verific$n140$168 [28] $verific$n140$168 [29] $verific$n140$168 [30] $verific$n140$168 [31] } New input vector for $reduce_or cell $verific$reduce_or_12$../../submodules/seu_ip/com_tr.sv:62$173: { $verific$n140$167 [0] $verific$n140$167 [1] $verific$n140$167 [2] $verific$n140$167 [3] $verific$n140$167 [4] $verific$n140$167 [5] $verific$n140$167 [6] $verific$n140$167 [7] $verific$n140$167 [8] $verific$n140$167 [9] $verific$n140$167 [10] $verific$n140$167 [11] $verific$n140$167 [12] $verific$n140$167 [13] $verific$n140$167 [14] $verific$n140$167 [15] $verific$n140$167 [16] $verific$n140$167 [17] $verific$n140$167 [18] $verific$n140$167 [19] $verific$n140$167 [20] $verific$n140$167 [21] $verific$n140$167 [22] $verific$n140$167 [23] $verific$n140$167 [24] $verific$n140$167 [25] $verific$n140$167 [26] $verific$n140$167 [27] $verific$n140$167 [28] $verific$n140$167 [29] $verific$n140$167 [30] $verific$n140$167 [31] }
Optimizing cells in module \com_tr(IN_WIDTH=32). Optimizing cells in module \com_tr(IN_WIDTH=32).
Optimizing cells in module \ham_reg. Optimizing cells in module \ham_reg.
Optimizing cells in module \hamming16t11d_dec. Optimizing cells in module \hamming16t11d_dec.
...@@ -320,7 +319,7 @@ Running muxtree optimizer on module \way3_voter.. ...@@ -320,7 +319,7 @@ Running muxtree optimizer on module \way3_voter..
Evaluating internal representation of mux trees. Evaluating internal representation of mux trees.
Analyzing evaluation results. Analyzing evaluation results.
Removed 0 multiplexer ports. Removed 0 multiplexer ports.
<suppressed ~21 debug messages> <suppressed ~20 debug messages>
12.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 12.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32). Optimizing cells in module \com_tr(IN_WIDTH=32).
...@@ -373,10 +372,10 @@ Optimizing module way3_voter. ...@@ -373,10 +372,10 @@ Optimizing module way3_voter.
12.6.16. Finished OPT passes. (There is nothing left to do.) 12.6.16. Finished OPT passes. (There is nothing left to do.)
12.7. Executing WREDUCE pass (reducing word size of cells). 12.7. Executing WREDUCE pass (reducing word size of cells).
Removed top 2 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_11$../../submodules/seu_ip/hamming16t11d_dec.sv:75$541 ($eq). Removed top 2 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_11$../../submodules/seu_ip/hamming16t11d_dec.sv:45$536 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_14$../../submodules/seu_ip/hamming16t11d_dec.sv:76$544 ($eq). Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_14$../../submodules/seu_ip/hamming16t11d_dec.sv:46$539 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_17$../../submodules/seu_ip/hamming16t11d_dec.sv:77$547 ($eq). Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_17$../../submodules/seu_ip/hamming16t11d_dec.sv:47$542 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_20$../../submodules/seu_ip/hamming16t11d_dec.sv:78$550 ($eq). Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_20$../../submodules/seu_ip/hamming16t11d_dec.sv:48$545 ($eq).
12.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 12.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
...@@ -526,10 +525,10 @@ Finding unused cells or wires in module \way3_voter.. ...@@ -526,10 +525,10 @@ Finding unused cells or wires in module \way3_voter..
=== sbf_reg(IN_WIDTH=32) === === sbf_reg(IN_WIDTH=32) ===
Number of wires: 10 Number of wires: 9
Number of wire bits: 165 Number of wire bits: 164
Number of public wires: 9 Number of public wires: 8
Number of public wire bits: 133 Number of public wire bits: 132
Number of memories: 0 Number of memories: 0
Number of memory bits: 0 Number of memory bits: 0
Number of processes: 0 Number of processes: 0
...@@ -540,16 +539,16 @@ Finding unused cells or wires in module \way3_voter.. ...@@ -540,16 +539,16 @@ Finding unused cells or wires in module \way3_voter..
=== triple_reg(IN_WIDTH=32) === === triple_reg(IN_WIDTH=32) ===
Number of wires: 18 Number of wires: 17
Number of wire bits: 390 Number of wire bits: 358
Number of public wires: 16 Number of public wires: 16
Number of public wire bits: 326 Number of public wire bits: 326
Number of memories: 0 Number of memories: 0
Number of memory bits: 0 Number of memory bits: 0
Number of processes: 0 Number of processes: 0
Number of cells: 5 Number of cells: 3
$dff 2 $dff 1
$mux 2 $mux 1
way3_voter 1 way3_voter 1
=== way3_voter === === way3_voter ===
...@@ -579,18 +578,18 @@ Finding unused cells or wires in module \way3_voter.. ...@@ -579,18 +578,18 @@ Finding unused cells or wires in module \way3_voter..
triple_reg(IN_WIDTH=32) 1 triple_reg(IN_WIDTH=32) 1
way3_voter 1 way3_voter 1
Number of wires: 117 Number of wires: 115
Number of wire bits: 1265 Number of wire bits: 1232
Number of public wires: 76 Number of public wires: 75
Number of public wire bits: 992 Number of public wire bits: 991
Number of memories: 0 Number of memories: 0
Number of memory bits: 0 Number of memory bits: 0
Number of processes: 0 Number of processes: 0
Number of cells: 77 Number of cells: 75
$and 1 $and 1
$dff 8 $dff 7
$eq 14 $eq 14
$mux 24 $mux 23
$ne 1 $ne 1
$not 13 $not 13
$reduce_bool 1 $reduce_bool 1
...@@ -692,7 +691,7 @@ Running muxtree optimizer on module \way3_voter.. ...@@ -692,7 +691,7 @@ Running muxtree optimizer on module \way3_voter..
Evaluating internal representation of mux trees. Evaluating internal representation of mux trees.
Analyzing evaluation results. Analyzing evaluation results.
Removed 0 multiplexer ports. Removed 0 multiplexer ports.
<suppressed ~21 debug messages> <suppressed ~20 debug messages>
14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32). Optimizing cells in module \com_tr(IN_WIDTH=32).
...@@ -719,8 +718,6 @@ Finding identical cells in module `\way3_voter'. ...@@ -719,8 +718,6 @@ Finding identical cells in module `\way3_voter'.
Removed a total of 0 cells. Removed a total of 0 cells.
14.6. Executing OPT_RMDFF pass (remove dff with constant values). 14.6. Executing OPT_RMDFF pass (remove dff with constant values).
Removing $verific$trip2_preg_reg$triple_reg.sv:62$189 ($dff) from module triple_reg(IN_WIDTH=32).
Replaced 1 DFF cells.
14.7. Executing OPT_CLEAN pass (remove unused cells and wires). 14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=32).. Finding unused cells or wires in module \com_tr(IN_WIDTH=32)..
...@@ -732,8 +729,6 @@ Finding unused cells or wires in module \reg_sbf.. ...@@ -732,8 +729,6 @@ Finding unused cells or wires in module \reg_sbf..
Finding unused cells or wires in module \sbf_reg(IN_WIDTH=32).. Finding unused cells or wires in module \sbf_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=32).. Finding unused cells or wires in module \triple_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \way3_voter.. Finding unused cells or wires in module \way3_voter..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>
14.8. Executing OPT_EXPR pass (perform const folding). 14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=32). Optimizing module com_tr(IN_WIDTH=32).
...@@ -746,95 +741,7 @@ Optimizing module sbf_reg(IN_WIDTH=32). ...@@ -746,95 +741,7 @@ Optimizing module sbf_reg(IN_WIDTH=32).
Optimizing module triple_reg(IN_WIDTH=32). Optimizing module triple_reg(IN_WIDTH=32).
Optimizing module way3_voter. Optimizing module way3_voter.
14.9. Rerunning OPT passes. (Maybe there is more to do..) 14.9. Finished OPT passes. (There is nothing left to do.)
14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=32)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \instances..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \reg_sbf..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \sbf_reg(IN_WIDTH=32)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=32)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~20 debug messages>
14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \com_tr(IN_WIDTH=32).
Optimizing cells in module \ham_reg.
Optimizing cells in module \hamming16t11d_dec.
Optimizing cells in module \hamming16t11d_enc.
Optimizing cells in module \instances.
Optimizing cells in module \reg_sbf.
Optimizing cells in module \sbf_reg(IN_WIDTH=32).
Optimizing cells in module \triple_reg(IN_WIDTH=32).
Optimizing cells in module \way3_voter.
Performed a total of 0 changes.
14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=32)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf'.
Finding identical cells in module `\sbf_reg(IN_WIDTH=32)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=32)'.
Finding identical cells in module `\way3_voter'.
Removed a total of 0 cells.
14.13. Executing OPT_RMDFF pass (remove dff with constant values).
14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=32)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf..
Finding unused cells or wires in module \sbf_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=32)..
Finding unused cells or wires in module \way3_voter..
14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=32).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
Optimizing module instances.
Optimizing module reg_sbf.
Optimizing module sbf_reg(IN_WIDTH=32).
Optimizing module triple_reg(IN_WIDTH=32).
Optimizing module way3_voter.
14.16. Finished OPT passes. (There is nothing left to do.)
15. Executing FSM pass (extract and optimize FSM). 15. Executing FSM pass (extract and optimize FSM).
...@@ -1518,7 +1425,7 @@ ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 3.1 -3.1 ps S = 1 ...@@ -1518,7 +1425,7 @@ ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 3.1 -3.1 ps S = 1
ABC: Path 1 -- 34 : 1 7 BUFX2 A = 2.35 Df = 56.4 -7.1 ps S = 42.3 ps Cin = 1.5 ff Cout = 17.8 ff Cmax = 518.7 ff G = 1078 ABC: Path 1 -- 34 : 1 7 BUFX2 A = 2.35 Df = 56.4 -7.1 ps S = 42.3 ps Cin = 1.5 ff Cout = 17.8 ff Cmax = 518.7 ff G = 1078
ABC: Path 2 -- 36 : 1 10 BUFX4 A = 2.82 Df = 99.6 -7.7 ps S = 32.7 ps Cin = 3.9 ff Cout = 22.9 ff Cmax = 999.3 ff G = 531 ABC: Path 2 -- 36 : 1 10 BUFX4 A = 2.82 Df = 99.6 -7.7 ps S = 32.7 ps Cin = 3.9 ff Cout = 22.9 ff Cmax = 999.3 ff G = 531
ABC: Path 3 -- 37 : 2 1 AND2X1 A = 2.35 Df = 126.6 -11.2 ps S = 23.7 ps Cin = 2.1 ff Cout = 0.0 ff Cmax = 137.4 ff G = 0 ABC: Path 3 -- 37 : 2 1 AND2X1 A = 2.35 Df = 126.6 -11.2 ps S = 23.7 ps Cin = 2.1 ff Cout = 0.0 ff Cmax = 137.4 ff G = 0
ABC: Start-point = pi1 (\rstn_i). End-point = po1 ($verific$n22$325 [2]). ABC: Start-point = pi1 (\rstn_i). End-point = po1 ($verific$n22$320 [2]).
ABC: + write_blif <abc-temp-dir>/output.blif ABC: + write_blif <abc-temp-dir>/output.blif
22.2.2. Re-integrating ABC results. 22.2.2. Re-integrating ABC results.
...@@ -1760,7 +1667,7 @@ ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 7.9 -4.9 ps S = 1 ...@@ -1760,7 +1667,7 @@ ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 7.9 -4.9 ps S = 1
ABC: Path 1 -- 66 : 1 5 BUFX4 A = 2.82 Df = 56.2 -21.1 ps S = 21.7 ps Cin = 3.9 ff Cout = 15.6 ff Cmax = 999.3 ff G = 392 ABC: Path 1 -- 66 : 1 5 BUFX4 A = 2.82 Df = 56.2 -21.1 ps S = 21.7 ps Cin = 3.9 ff Cout = 15.6 ff Cmax = 999.3 ff G = 392
ABC: Path 2 -- 68 : 1 10 BUFX4 A = 2.82 Df = 103.1 -31.3 ps S = 31.7 ps Cin = 3.9 ff Cout = 22.9 ff Cmax = 999.3 ff G = 531 ABC: Path 2 -- 68 : 1 10 BUFX4 A = 2.82 Df = 103.1 -31.3 ps S = 31.7 ps Cin = 3.9 ff Cout = 22.9 ff Cmax = 999.3 ff G = 531
ABC: Path 3 -- 69 : 2 1 AND2X1 A = 2.35 Df = 129.0 -33.8 ps S = 23.7 ps Cin = 2.1 ff Cout = 0.0 ff Cmax = 137.4 ff G = 0 ABC: Path 3 -- 69 : 2 1 AND2X1 A = 2.35 Df = 129.0 -33.8 ps S = 23.7 ps Cin = 2.1 ff Cout = 0.0 ff Cmax = 137.4 ff G = 0
ABC: Start-point = pi1 (\rstn_i). End-point = po1 ($verific$n39$388 [2]). ABC: Start-point = pi1 (\rstn_i). End-point = po1 ($verific$n39$383 [2]).
ABC: + write_blif <abc-temp-dir>/output.blif ABC: + write_blif <abc-temp-dir>/output.blif
22.7.2. Re-integrating ABC results. 22.7.2. Re-integrating ABC results.
...@@ -1815,7 +1722,7 @@ ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 7.9 -4.9 ps S = 1 ...@@ -1815,7 +1722,7 @@ ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 7.9 -4.9 ps S = 1
ABC: Path 1 -- 66 : 1 5 BUFX4 A = 2.82 Df = 56.2 -21.1 ps S = 21.7 ps Cin = 3.9 ff Cout = 15.6 ff Cmax = 999.3 ff G = 392 ABC: Path 1 -- 66 : 1 5 BUFX4 A = 2.82 Df = 56.2 -21.1 ps S = 21.7 ps Cin = 3.9 ff Cout = 15.6 ff Cmax = 999.3 ff G = 392
ABC: Path 2 -- 68 : 1 10 BUFX4 A = 2.82 Df = 103.1 -31.3 ps S = 31.7 ps Cin = 3.9 ff Cout = 22.9 ff Cmax = 999.3 ff G = 531 ABC: Path 2 -- 68 : 1 10 BUFX4 A = 2.82 Df = 103.1 -31.3 ps S = 31.7 ps Cin = 3.9 ff Cout = 22.9 ff Cmax = 999.3 ff G = 531
ABC: Path 3 -- 69 : 2 1 AND2X1 A = 2.35 Df = 129.0 -33.8 ps S = 23.7 ps Cin = 2.1 ff Cout = 0.0 ff Cmax = 137.4 ff G = 0 ABC: Path 3 -- 69 : 2 1 AND2X1 A = 2.35 Df = 129.0 -33.8 ps S = 23.7 ps Cin = 2.1 ff Cout = 0.0 ff Cmax = 137.4 ff G = 0
ABC: Start-point = pi1 (\rstn_i). End-point = po1 ($verific$n138$178 [2]). ABC: Start-point = pi1 (\rstn_i). End-point = po1 ($verific$n138$176 [2]).
ABC: + write_blif <abc-temp-dir>/output.blif ABC: + write_blif <abc-temp-dir>/output.blif
22.8.2. Re-integrating ABC results. 22.8.2. Re-integrating ABC results.
...@@ -2023,10 +1930,10 @@ Removing temp directory. ...@@ -2023,10 +1930,10 @@ Removing temp directory.
=== sbf_reg(IN_WIDTH=32) === === sbf_reg(IN_WIDTH=32) ===
Number of wires: 79 Number of wires: 78
Number of wire bits: 234 Number of wire bits: 233
Number of public wires: 9 Number of public wires: 8
Number of public wire bits: 133 Number of public wire bits: 132
Number of memories: 0 Number of memories: 0
Number of memory bits: 0 Number of memory bits: 0
Number of processes: 0 Number of processes: 0
...@@ -2098,10 +2005,10 @@ Removing temp directory. ...@@ -2098,10 +2005,10 @@ Removing temp directory.
triple_reg(IN_WIDTH=32) 1 triple_reg(IN_WIDTH=32) 1
way3_voter 1 way3_voter 1
Number of wires: 1135 Number of wires: 1134
Number of wire bits: 2563 Number of wire bits: 2562
Number of public wires: 76 Number of public wires: 75
Number of public wire bits: 992 Number of public wire bits: 991
Number of memories: 0 Number of memories: 0
Number of memory bits: 0 Number of memory bits: 0
Number of processes: 0 Number of processes: 0
...@@ -2138,7 +2045,7 @@ Dumping module `\sbf_reg(IN_WIDTH=32)'. ...@@ -2138,7 +2045,7 @@ Dumping module `\sbf_reg(IN_WIDTH=32)'.
Dumping module `\triple_reg(IN_WIDTH=32)'. Dumping module `\triple_reg(IN_WIDTH=32)'.
Dumping module `\way3_voter'. Dumping module `\way3_voter'.
End of script. Logfile hash: 3654bc7017 End of script. Logfile hash: f153875eb6
CPU: user 0.32s system 0.01s, MEM: 141.18 MB total, 24.98 MB resident CPU: user 0.31s system 0.02s, MEM: 141.29 MB total, 25.06 MB resident
Yosys 0.8+472 (git sha1 c907899, clang 3.8.0-2ubuntu4 -fPIC -Os) Yosys 0.8+472 (git sha1 c907899, clang 3.8.0-2ubuntu4 -fPIC -Os)
Time spent: 19% 2x write_verilog (0 sec), 16% 15x opt_expr (0 sec), ... Time spent: 19% 2x write_verilog (0 sec), 16% 14x opt_expr (0 sec), ...
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questa_sim/Makefile
questa_sim/PMU_raw/
questa_sim/modelsim.ini
questa_sim/tb_axi_pmu/AXI_PMU/
questa_sim/tb_pmu_ahb/pmu_ahb/
questa_sim/tb_pmu_raw/PMU_raw/
MCCU/ MCCU
MCCU_test.vcd
Makefile Makefile
modelsim.ini modelsim.ini
test.vcd
transcript transcript
vsim.wlf vsim.wlf
#$1 #$1
TOP=../../../
if [ -z "$1" ] if [ -z "$1" ]
then then
vlib MCCU vlib MCCU
vmap work $PWD/MCCU vmap work $PWD/MCCU
vlog +acc=rn +incdir+../../hdl/ ../../hdl/*.sv tb_MCCU.sv vlog +acc=rn +incdir+$TOP/hdl/ $TOP/hdl/*.sv $TOP/submodules/seu_ip/way3*.sv tb_MCCU.sv
vmake MCCU/ > Makefile vmake MCCU/ > Makefile
vsim work.tb_MCCU -do "view wave -new" -do "do wave.do" -do "run -all" vsim work.tb_MCCU -do "view wave -new" -do "do wave.do" -do "run -all"
else else
vlib MCCU vlib MCCU
vmap work $PWD/MCCU vmap work $PWD/MCCU
vlog +acc=rn +incdir+../../hdl/ ../../hdl/*.sv tb_MCCU.sv vlog +acc=rn +incdir+$TOP/hdl/ $TOP/hdl/*.sv $TOP/submodules/seu_ip/way3*.sv tb_MCCU.sv
vmake MCCU/ > Makefile vmake MCCU/ > Makefile
vsim work.tb_MCCU $1 -do "do save_wave.do" vsim work.tb_MCCU $1 -do "do save_wave.do"
fi fi