Commit 3b9dca18 authored by Pablo Andreu's avatar Pablo Andreu
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Added support for disabling randomizer and leaky

Now leaky bucket is really leaky bucket.
Now quota refill is as the name says.
Now disabling random refill periods is possible.
parent a12909b5
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...@@ -161,7 +161,7 @@ ...@@ -161,7 +161,7 @@
//---- Total of registers used //---- Total of registers used
localparam integer TOTAL_NREGS = localparam integer TOTAL_NREGS =
N_COUNTERS + N_CONF_REGS + N_OVERFLOW_REGS N_COUNTERS + N_CONF_REGS + N_OVERFLOW_REGS
+N_QUOTA_REGS + N_MCCU_REGS + N_RDC_REGS + N_CROSSBAR_REGS+1 +N_QUOTA_REGS + N_MCCU_REGS + N_RDC_REGS + N_CROSSBAR_REGS+2
) )
( (
// Global Clock Signal // Global Clock Signal
...@@ -518,8 +518,16 @@ end ...@@ -518,8 +518,16 @@ end
assign regs_o[47] = regs_i[47]; assign regs_o[47] = regs_i[47];
wire[31:0] quotaResetPeriod; wire[31:0] quotaResetPeriod;
assign quotaResetPeriod = regs_i[47]; assign quotaResetPeriod = regs_i[47];
assign regs_o[48] = regs_i[48];
wire[31:0] quotaLeakyRefillValue;
assign quotaLeakyRefillValue = regs_i[48];
wire enableQuotaRefill;
assign enableQuotaRefill = regs_i[BASE_MCCU_CFG][8];
wire enableLeakyBucket; wire enableLeakyBucket;
assign enableLeakyBucket = regs_i[BASE_MCCU_CFG][8]; assign enableLeakyBucket = regs_i[BASE_MCCU_CFG][9];
wire enableQuotaRng;
assign enableQuotaRng = regs_i[BASE_MCCU_CFG][10];
//register enable to solve Hazards //register enable to solve Hazards
reg MCCU_rstn; reg MCCU_rstn;
...@@ -564,8 +572,11 @@ end ...@@ -564,8 +572,11 @@ end
// Individual interrupts allow each core to // Individual interrupts allow each core to
// handle their own interrupts , therefore // handle their own interrupts , therefore
//it seems to be te right solution. //it seems to be te right solution.
.quotaResetPeriod (quotaResetPeriod), .quotaResetPeriod (quotaResetPeriod),
.enableLeakyBucket (enableLeakyBucket) .quotaLeakyRefillValue (quotaLeakyRefillValue),
.enableQuotaRefill (enableQuotaRefill),
.enableLeakyBucket (enableLeakyBucket),
.enableQuotaRng (enableQuotaRng)
); );
//---------------------------------------------- //----------------------------------------------
......
...@@ -51,7 +51,10 @@ ...@@ -51,7 +51,10 @@
//Quota interruption //Quota interruption
output wire interruption_quota_o[N_CORES-1:0], output wire interruption_quota_o[N_CORES-1:0],
input wire [DATA_WIDTH-1:0] quotaResetPeriod, input wire [DATA_WIDTH-1:0] quotaResetPeriod,
input wire enableLeakyBucket input wire [DATA_WIDTH-1:0] quotaLeakyRefillValue,
input wire enableQuotaRefill,
input wire enableLeakyBucket,
input wire enableQuotaRng
); );
...@@ -70,7 +73,13 @@ ...@@ -70,7 +73,13 @@
assign outputRNGMask[z] = quotaResetPeriodScaled[z] | outputRNGMask[z+1]; assign outputRNGMask[z] = quotaResetPeriodScaled[z] | outputRNGMask[z+1];
end end
assign quotaResetPeriodRandomized = outputRNG & outputRNGMask; //This is a hacky way of doing this, renaming this variable to represent its real meaning would be the best
assign quotaResetPeriodRandomized = enableQuotaRng ? (outputRNG & outputRNGMask) : quotaResetPeriod;
// if(enableQuotaRng) begin
// assign quotaResetPeriodRandomized = outputRNG & outputRNGMask;
// end else begin
// assign quotaResetPeriodRandomized = quotaResetPeriod;
// end
LFSR #( LFSR #(
.NUM_BITS(DATA_WIDTH) .NUM_BITS(DATA_WIDTH)
...@@ -91,7 +100,7 @@ ...@@ -91,7 +100,7 @@
for(i=0; i < N_CORES; i++)begin for(i=0; i < N_CORES; i++)begin
cycleCounter[i] <= 0; cycleCounter[i] <= 0;
end end
end else if(enableLeakyBucket && enable_i) begin end else if(enableQuotaRefill && enable_i) begin
for(i=0; i < N_CORES; i++) begin for(i=0; i < N_CORES; i++) begin
if((interruption_quota_o[i] == 1) && cycleCounter[i] < quotaResetPeriodRandomizedRegistered[i]) begin if((interruption_quota_o[i] == 1) && cycleCounter[i] < quotaResetPeriodRandomizedRegistered[i]) begin
cycleCounter[i] <= cycleCounter[i]+1; cycleCounter[i] <= cycleCounter[i]+1;
...@@ -223,13 +232,13 @@ ...@@ -223,13 +232,13 @@
//!Enable && !update: hold values quota_int //!Enable && !update: hold values quota_int
if(!enable_i && !update_quota_i[i]) begin if(!enable_i && !update_quota_i[i]) begin
quota_int[i] <= quota_int[i]; quota_int[i] <= quota_int[i];
//!Enable && update: Update values quota_int with quota_i, // !Enable && update: Update values quota_int with quota_i,
// do NOT substract // do NOT substract
end else if (!enable_i && update_quota_i[i]) begin end else if (!enable_i && update_quota_i[i]) begin
quota_int[i] <= quota_i[i]; quota_int[i] <= quota_i[i];
//Enable && !update:Replace quota_int with quota_int minus //Enable && !update:Replace quota_int with quota_int minus
// consumed quota (ccc_quota) // consumed quota (ccc_quota)
end else if (enable_i && !update_quota_i[i] && !(enableLeakyBucket && (cycleCounter[i] == quotaResetPeriodRandomizedRegistered[i]))) begin end else if (enable_i && !update_quota_i[i] && !(enableQuotaRefill && (cycleCounter[i] == quotaResetPeriodRandomizedRegistered[i]))) begin
for (j=0; j<CORE_EVENTS; j=j+1) begin for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for //underflow detection. Padding needed for
// prevent width mismatch // prevent width mismatch
...@@ -242,7 +251,22 @@ ...@@ -242,7 +251,22 @@
end end
//Enable && update: Update values quota_int with quota_i and //Enable && update: Update values quota_int with quota_i and
// substract ccc_quota // substract ccc_quota
end else if(enable_i && (update_quota_i[i] || (enableLeakyBucket && (cycleCounter[i] == quotaResetPeriodRandomizedRegistered[i]))))begin end else if(enable_i && (update_quota_i[i] || (enableQuotaRefill && (cycleCounter[i] == quotaResetPeriodRandomizedRegistered[i]))))begin
for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for
// prevent width mismatch
if( ccc_suma_int[i] > {{O_D_0PAD{1'b0}},quota_i[i]} )
begin
quota_int[i] <={DATA_WIDTH{1'b0}};
end else begin
if(enableLeakyBucket) begin
quota_int[i] <= quotaLeakyRefillValue - ccc_suma_int[i][DATA_WIDTH-1:0];
end else begin
quota_int[i] <= quota_i[i] - ccc_suma_int[i][DATA_WIDTH-1:0];
end
end
end
/* end else if(enable_i && (update_quota_i[i] || (enableLeakyBucket && (cycleCounter[i] == quotaResetPeriodRandomizedRegistered[i]))))begin
for (j=0; j<CORE_EVENTS; j=j+1) begin for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for //underflow detection. Padding needed for
// prevent width mismatch // prevent width mismatch
...@@ -252,7 +276,7 @@ ...@@ -252,7 +276,7 @@
end else begin end else begin
quota_int[i] <= quota_i[i] - ccc_suma_int[i][DATA_WIDTH-1:0]; quota_int[i] <= quota_i[i] - ccc_suma_int[i][DATA_WIDTH-1:0];
end end
end end*/
end end
end end
/*---------- /*----------
...@@ -329,7 +353,7 @@ ...@@ -329,7 +353,7 @@
for(x=0; x<N_CORES; x=x+1) begin: InterruptionQuotaHold for(x=0; x<N_CORES; x=x+1) begin: InterruptionQuotaHold
always @(posedge clk_i) begin always @(posedge clk_i) begin
if(rstn_i == 1'b0 | (enableLeakyBucket & (cycleCounter[x] == quotaResetPeriodRandomizedRegistered[x]))) begin if(rstn_i == 1'b0 | (enableQuotaRefill & (cycleCounter[x] == quotaResetPeriodRandomizedRegistered[x]))) begin
interruption_quota_q[x] <= '0; interruption_quota_q[x] <= '0;
end else begin end else begin
interruption_quota_q[x] <= interruption_quota_d[x] | interruption_quota_q[x]; interruption_quota_q[x] <= interruption_quota_d[x] | interruption_quota_q[x];
......
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