Commit 3179bb5d authored by Guillem's avatar Guillem
Browse files

Added interruption from MCCU

They will kill execution of pwd
parent 42a3168d
#include <stdlib.h>
#include <stdint.h>
//ICACHE L1
#define L1I_WAYS 4
#define L1I_SETS 64
#define L1I_LINE 128/8*4 //bytes
#define L1I_SIZE L1_WAYS*L1_SETS*L1_LINE //bytes
//DCACHE L1
#define L1D_WAYS 4
#define L1D_SETS 64
#define L1D_LINE 128/8*4 //bytes
#define L1D_SIZE L1_WAYS*L1_SETS*L1_LINE //bytes
//CACHE L2
//Write alocate
//Inclusive, L2 evicts L1
//Interleaved access to the banks
//Replace policy, random
#define L2_BANKS 2
#define L2_WAYS 8
#define L2_SETS 256
#define L2_LINE 128/8*4 //bytes
#define L2_SIZE L2_BANKS*L2_WAYS*L2_SETS*L2_LINE //bytes
//Strides
#define L1D_WAY_STRIDE = L1D_SIZE/L1D_WAYS
#define L1D_LINE_STRIDE = L1D_LINE
#define L2_WAY_STRIDE = L2_SIZE/L2_WAYS
#define L2_LINE_STRIDE = L2_LINE
//Range of addresses were mem ops are issued shall be the size of L2
#define RANGE = L2_SIZE
//Define iterations assembly loop
#define iterations 1000
/*
//Generate an array with the range of memory that we want to acces
void gen_acces_seq(void){
//To get the full Range of stores in L2
//Way stride = 8192 bytes 2048 32b words, Offset Address 0x00 to 0x800 | 2048
//Line stride = 16 bytes 4 words, Offset Address 0x00 to 0xc
//L2 size = 65536 bytes . 6384 32b words, Offset Address 0x00 to 0x18f0 | 6384
uint32_t array_size= 6384;// number of words
uint32_t [array_size] array;//define array of addresses
//fill all the array
array[0]=0;
for (int i=1; i<array_size; i++){
array[i] = array[i-1]+L2_LINE_STRIDE;
}
}*/
void cont_hitL2_load(void)
{
asm (
"addi t0, x0, 8" "\n\t" //since L2_WAYS happen to be 2048bytes each
// "lui t1, 1" "\n\t"//place initial adress for t1 = 0xF000
"lui t1, 0x70000" "\n\t"//place initial adress for t1 = 0xF000
"cont_start:" "\n\t"
"lw a0, 0(t1)" "\n\t"
"lw a0, 64(t1)" "\n\t"
"lw a0, 128(t1)" "\n\t"
"lw a0, 192(t1)" "\n\t"
"lw a0, 256(t1)" "\n\t"
"lw a0, 320(t1)" "\n\t"
"lw a0, 384(t1)" "\n\t"
"lw a0, 448(t1)" "\n\t"
"lw a0, 512(t1)" "\n\t"
"lw a0, 576(t1)" "\n\t"
"lw a0, 640(t1)" "\n\t"
"lw a0, 704(t1)" "\n\t"
"lw a0, 768(t1)" "\n\t"
"lw a0, 832(t1)" "\n\t"
"lw a0, 896(t1)" "\n\t"
"lw a0, 960(t1)" "\n\t"
"lw a0, 1024(t1)" "\n\t"
"lw a0, 1088(t1)" "\n\t"
"lw a0, 1152(t1)" "\n\t"
"lw a0, 1216(t1)" "\n\t"
"lw a0, 1280(t1)" "\n\t"
"lw a0, 1344(t1)" "\n\t"
"lw a0, 1408(t1)" "\n\t"
"lw a0, 1472(t1)" "\n\t"
"lw a0, 1536(t1)" "\n\t"
"lw a0, 1600(t1)" "\n\t"
"lw a0, 1664(t1)" "\n\t"
"lw a0, 1728(t1)" "\n\t"
"lw a0, 1792(t1)" "\n\t"
"lw a0, 1856(t1)" "\n\t"
"lw a0, 1920(t1)" "\n\t"
"lw a0, 1984(t1)" "\n\t"
"addi t1, t1, -2048" "\n\t"
"addi t0, t0, -1" "\n\t"
"bgtz t0, cont_start" "\n\t"
);
}
...@@ -216,7 +216,7 @@ int main( int argc, char* argv[] ) ...@@ -216,7 +216,7 @@ int main( int argc, char* argv[] )
// Print out the results // Print out the results
printArray( "test", DATA_SIZE, input_data ); printArray( "test", DATA_SIZE, input_data );
disable_PMU_32b(); // disable_PMU_32b();
// Check the results // Check the results
return verify( DATA_SIZE, input_data, verify_data ); return verify( DATA_SIZE, input_data, verify_data );
} }
[*] [*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Mon Nov 11 12:07:39 2019 [*] Tue Nov 12 11:10:16 2019
[*] [*]
[dumpfile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/vsim/qsort100.vcd" [dumpfile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/vsim/qsort100.vcd"
[dumpfile_mtime] "Mon Nov 11 12:03:52 2019" [dumpfile_mtime] "Tue Nov 12 11:09:22 2019"
[dumpfile_size] 231013831 [dumpfile_size] 201950538
[savefile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/tb/verilator/testSOC.gtkw" [savefile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/tb/verilator/testSOC.gtkw"
[timestart] 0 [timestart] 0
[size] 1920 1052 [size] 1920 1052
[pos] 0 2 [pos] 0 2
*-13.057642 31750 16295 112420 237330 113990 241080 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-16.057642 31750 16295 112420 237330 113990 241080 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP. [treeopen] TOP.
[treeopen] TOP.chip_top. [treeopen] TOP.chip_top.
[treeopen] TOP.chip_top.AXI_PMU_0. [treeopen] TOP.chip_top.AXI_PMU_0.
...@@ -19,7 +19,6 @@ ...@@ -19,7 +19,6 @@
[treeopen] TOP.chip_top.io_nasti_mem. [treeopen] TOP.chip_top.io_nasti_mem.
[treeopen] TOP.chip_top.mem_nasti. [treeopen] TOP.chip_top.mem_nasti.
[treeopen] TOP.chip_top.Rocket. [treeopen] TOP.chip_top.Rocket.
[treeopen] TOP.chip_top.Rocket.RocketTile.
[treeopen] TOP.chip_top.Rocket.RocketTile.cache. [treeopen] TOP.chip_top.Rocket.RocketTile.cache.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR. [treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.BIP. [treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.BIP.
...@@ -30,14 +29,13 @@ ...@@ -30,14 +29,13 @@
[treeopen] TOP.chip_top.Rocket.RocketTile.dcache.dtlb. [treeopen] TOP.chip_top.Rocket.RocketTile.dcache.dtlb.
[treeopen] TOP.chip_top.Rocket.RocketTile.dcache.mshrs. [treeopen] TOP.chip_top.Rocket.RocketTile.dcache.mshrs.
[treeopen] TOP.chip_top.Rocket.RocketTile.ptw. [treeopen] TOP.chip_top.Rocket.RocketTile.ptw.
[treeopen] TOP.chip_top.Rocket.RocketTile_1.
[treeopen] TOP.chip_top.Rocket.RocketTile_1.core. [treeopen] TOP.chip_top.Rocket.RocketTile_1.core.
[treeopen] TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE. [treeopen] TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.
[treeopen] TOP.chip_top.Rocket.RocketTile_1.dcache. [treeopen] TOP.chip_top.Rocket.RocketTile_1.dcache.
[sst_width] 422 [sst_width] 422
[signals_width] 374 [signals_width] 437
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 488 [sst_vpaned_height] 504
@22 @22
[color] 3 [color] 3
TOP.clk_n TOP.clk_n
...@@ -419,7 +417,6 @@ TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.lock ...@@ -419,7 +417,6 @@ TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.lock
TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.read_addr[4:0] TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.read_addr[4:0]
TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.read_data[63:0] TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.read_data[63:0]
TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.write_addr[4:0] TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.write_addr[4:0]
@23
TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.write_data[63:0] TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.write_data[63:0]
@28 @28
TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.write_enable TOP.chip_top.Rocket.RocketTile_1.core.INT_REGISTER_FILE.BANK_1.write_enable
...@@ -446,10 +443,16 @@ TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_ma_ld ...@@ -446,10 +443,16 @@ TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_ma_ld
TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_ma_st TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_ma_st
TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_pf_ld TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_pf_ld
TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_pf_st TOP.chip_top.Rocket.RocketTile.dcache_io_cpu_xcpt_pf_st
TOP.chip_top.pmu_intr_overflow
TOP.chip_top.pmu_intr_quota
@29
[color] 1
TOP.chip_top.pmu_intr_quota_c0
[color] 1
TOP.chip_top.pmu_intr_quota_c1
[color] 1
TOP.chip_top.Rocket.RocketTile.io_PMU_MCCU_intr
[color] 1
TOP.chip_top.Rocket.RocketTile_1.io_PMU_MCCU_intr
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
!100000@@
?"E68
@c00023
TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
!!
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Thu Sep 19 13:24:37 2019
[*]
[dumpfile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/vsim/write_test.vcd"
[dumpfile_mtime] "Thu Sep 19 13:18:15 2019"
[dumpfile_size] 62536056
[savefile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/tb/verilator/testSOC_bkp.gtkw"
[timestart] 0
[size] 1920 1025
[pos] 0 0
*-13.000000 3150 16295 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.chip_top.
[treeopen] TOP.chip_top.AXI_PMU_0.
[treeopen] TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.
[treeopen] TOP.chip_top.io_nasti.
[treeopen] TOP.chip_top.io_nasti_cbo.
[treeopen] TOP.chip_top.io_nasti_mem.
[treeopen] TOP.chip_top.mem_nasti.
[treeopen] TOP.chip_top.Rocket.
[treeopen] TOP.chip_top.Rocket.RocketTile.
[treeopen] TOP.chip_top.Rocket.RocketTile.cache.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.BIP.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.BTB.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.BIMODAL_PREDICTOR.PHT.
[treeopen] TOP.chip_top.Rocket.RocketTile.core.FETCH.
[treeopen] TOP.chip_top.Rocket.RocketTile.dcache.
[treeopen] TOP.chip_top.Rocket.RocketTile.dcache.dtlb.
[treeopen] TOP.chip_top.Rocket.RocketTile.ptw.
[sst_width] 422
[signals_width] 238
[sst_expanded] 1
[sst_vpaned_height] 391
@22
[color] 3
TOP.clk_n
@28
TOP.chip_top.Rocket.RocketTile.core.EXE_PC_VALID
@29
TOP.chip_top.Rocket.RocketTile.core.EXE_INT_UNIT_VALID
@804022
^>1 /home/bscuser/BSC/lowrisc/gtkwave/RISC-V_DISASSEMBLER.o
#{Full_OP} (0)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (1)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (2)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (3)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (4)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (5)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (6)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0] (1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0] (2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0] (0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (3)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (4)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (5)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (6)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0]
@c00022
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(3)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(4)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(5)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(6)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
@1401200
-group_end
@c00022
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
@1401200
-group_end
@22
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0]
@1001200
-group_end
@c00022
TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(3)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(4)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(5)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(6)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(7)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(8)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(9)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(10)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(11)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(12)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(13)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(14)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(15)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(16)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(17)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(18)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(19)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(20)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(21)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(22)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(23)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(24)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(25)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(26)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(27)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(28)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(29)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(30)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(31)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(32)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(33)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(34)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(35)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(36)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(37)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(38)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
(39)TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
@1401200
-group_end
@c00022
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(3)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(4)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(5)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(6)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
@1401200
-group_end
@22
TOP.chip_top.Rocket.RocketTile.core.IMM12_BRANCH[11:0]
TOP.chip_top.Rocket.RocketTile.core.IMM12_INT[11:0]
TOP.chip_top.Rocket.RocketTile.core.IMM20_INT[19:0]
@c00022
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
@1401200
-group_end
@22
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0]
@c00200
-IO_NASTI write response
@22
[color] 2
TOP.chip_top.io_nasti.b_id[8:0]
@28
[color] 2
TOP.chip_top.io_nasti.b_ready[0]
[color] 2
TOP.chip_top.io_nasti.b_resp[1:0]
[color] 2
TOP.chip_top.io_nasti.b_user[0]
[color] 2
TOP.chip_top.io_nasti.b_valid[0]
@1401200
-IO_NASTI write response
@800200
-IO_NASTI write writeaddr
@22
[color] 2
TOP.chip_top.io_nasti.aw_addr[31:0]
@28
[color] 2
TOP.chip_top.io_nasti.aw_valid[0]
[color] 2
TOP.chip_top.io_nasti.aw_ready[0]
[color] 2
TOP.chip_top.io_nasti.w_valid[0]
[color] 2
TOP.chip_top.io_nasti.w_ready[0]
@22
[color] 2
TOP.chip_top.io_nasti.w_data[31:0]
[color] 2
TOP.chip_top.io_nasti.w_strb[3:0]
@1000200
-IO_NASTI write writeaddr
@800200
-PMU signals and sources
@28
[color] 1
+{ICACHE_s2_miss} TOP.chip_top.Rocket.RocketTile.cache.icache.s2_miss
[color] 1
+{ITLB_miss} TOP.chip_top.Rocket.RocketTile.cache.tlb.tlb_miss
[color] 3
+{DCHACHE_s2_nack_miss} TOP.chip_top.Rocket.RocketTile.dcache.s2_nack_miss
[color] 1
+{DTLB_miss} TOP.chip_top.Rocket.RocketTile.dcache.dtlb.tlb_miss
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_LOAD
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_STORE
[color] 1
TOP.chip_top.Rocket.RocketTile.core.FETCH.EXE_MISS_PREDICTION
@22
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
@28
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_PC_VALID
@1000200
-PMU signals and sources
@c04022
^>1 /home/bscuser/BSC/lowrisc/gtkwave/RISC-V_DISASSEMBLER.o
#{Full_OP} (0)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (1)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (2)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (3)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (4)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (5)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (6)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0] (0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0] (1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0] (2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0] (0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (3)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (4)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (5)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0] (6)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0]
@28
TOP.chip_top.Rocket.RocketTile.core.EXE_PC_VALID
@c00022
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(3)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(4)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(5)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
(6)TOP.chip_top.Rocket.RocketTile.core.EXE_OPCODE[6:0]
@1401200
-group_end
@c00022
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
@28
(0)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
(1)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
(2)TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT3[2:0]
@1401200
-group_end
@22
[color] 1
TOP.chip_top.Rocket.RocketTile.core.EXE_FUNCT7[6:0]
@1401200
-group_end
@22
TOP.chip_top.Rocket.RocketTile.core.previous_EXE_PC[39:0]
TOP.chip_top.Rocket.RocketTile.core.previous_EXE_PC[39:0]
TOP.chip_top.Rocket.RocketTile.core.EXE_PC[39:0]
@28
TOP.chip_top.Rocket.RocketTile.core.EXE_PC_VALID
TOP.chip_top.Rocket.RocketTile.core.new_instruction
[color] 1
TOP.chip_top.new_instruction_c0
[color] 2
TOP.chip_top.clk
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(0)[31:0]
@28
TOP.chip_top.icache_miss_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(1)[31:0]
@28
TOP.chip_top.itlb_miss_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(2)[31:0]
@28
TOP.chip_top.dcache_miss_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(3)[31:0]
@28
[color] 1
+{DTLB_miss} TOP.chip_top.Rocket.RocketTile.dcache.dtlb.tlb_miss
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(4)[31:0]
@28
TOP.chip_top.EXE_STORE_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(5)[31:0]
@28
TOP.chip_top.EXE_LOAD_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(7)[31:0]
@28
[color] 1
TOP.chip_top.new_instruction_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(0)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(1)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(2)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(3)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(4)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(5)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(6)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(7)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(8)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(9)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(10)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(11)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(12)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(13)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(14)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(15)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(16)[31:0]
@200
-PMU_main_cfg
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(17)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(18)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(19)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(20)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(21)[31:0]
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(22)[31:0]
@200
-PMU_quota_mask
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(23)[31:0]
@200
-PMU_quota_limit
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(24)[31:0]
@200
-MCCU_main_cfg
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(25)[31:0]
@200
-MCCU_quota_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(26)[31:0]
@200
-MCCU_quota_c1
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(27)[31:0]
@200
-MCCU_weights_0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(28)[31:0]
@200
-MCCU_weights_1
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(29)[31:0]
@200
-MCCU_remaining_quota_c0
@22
TOP.chip_top.AXI_PMU_0.inst_AXI_PMU.slv_reg(30)[31:0]
@200
-MCCU_remaining_quota_c1
@22
TOP.chip_top.AXI_PMU_0.S_AXI_ARADDR_i[27:0]
TOP.chip_top.AXI_PMU_0.S_AXI_AWADDR_i[27:0]
@28
TOP.chip_top.Rocket.io_AXI_PMUc1_EXE_LOAD
TOP.chip_top.Rocket.io_AXI_PMUc1_EXE_STORE
TOP.chip_top.Rocket.io_AXI_PMUc1_branch_miss
TOP.chip_top.Rocket.io_AXI_PMUc1_dcache_miss
TOP.chip_top.Rocket.io_AXI_PMUc1_dtlb_miss
TOP.chip_top.Rocket.io_AXI_PMUc1_icache_miss
TOP.chip_top.Rocket.io_AXI_PMUc1_itlb_miss
TOP.chip_top.Rocket.io_AXI_PMUc1_new_instruction
TOP.chip_top.Rocket.RocketTile.io_PMU_EXE_LOAD
TOP.chip_top.Rocket.RocketTile.io_PMU_EXE_STORE
TOP.chip_top.Rocket.RocketTile.io_PMU_branch_miss
TOP.chip_top.Rocket.RocketTile.io_PMU_dcache_miss
TOP.chip_top.Rocket.RocketTile.io_PMU_dtlb_miss
TOP.chip_top.Rocket.RocketTile.io_PMU_icache_miss
TOP.chip_top.Rocket.RocketTile.io_PMU_itlb_miss
TOP.chip_top.Rocket.RocketTile.io_PMU_new_instruction
TOP.chip_top.Rocket.RocketTile.dcache.io_cpu_req_ready
TOP.chip_top.Rocket.RocketTile.dcache.io_cpu_req_valid
[pattern_trace] 1
[pattern_trace] 0
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