Commit 30a05809 authored by GuillemCabo's avatar GuillemCabo
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add MCCU specs and code comments

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\section{General purpose of the module}
MCCU stands for maximum-contention control unit, and aims to measure resource access an enforce the maximum contention produced for different cores in a multi-core system. Further details about the initial concept are provided by the paper \href{https://upcommons.upc.edu/handle/2117/133656}{Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement}, implementation may vary.\\
\\
The MCCU is allowed to assign individual quotas for each core. The quota value represent the number of clock cycles that the corresponding core is allowed to cause contention over other cores. At setup the user assigns weights to each one of the MCCU signals, the content of the weight would be the average or worst contention that a given event can cause over other cores, is up to the user to set the appropiate value for the end application. While the unit is enabled, at each clock cycle checks all the active events and adds its corresponding weights. In the same cycle the result of the weight addition is subtracted from the core quota. When the quota is about to reach 0 an interrupt is risen.\\
\\
Interruptions can be handled individually for each core, rather than relaying on a monitor core, but that is dependent of the target platform.
\ No newline at end of file
\section{Design placement}
\label{chapter2}
This modules is meant to be instantiated by the interface agnostic PMU (PMU\_raw.sv). Only one instance of this module is required.
%This module is meant to be a blackbox inside the chisel code. It belongs to the Drac class in the \emph{rocket.scala} file. We can have as many instances of this module as cores are instantiated in the SoC. Currently only single core operation has been tested.
\section{Parameters}
\label{chapter3}
This unit uses several parameters. \textbf{DATA\_WIDTH} defines the size of the data registers.\\
\textbf{WEIGHTS\_WIDTH} defines the size of the registers that store the estimated contention that a given event causes.\textbf{ N\_CORES} is used to configured to replicate the internal logic of the RDC to support several cores. \textbf{CORE\_EVENTS} sets the number of events that are track for each core.\\
\\
Internal parameters are used to perform padding between signals of different width when need to be used together. Such local parameter are\textbf{ O\_D\_0PAD, D\_W\_0PAD, O\_W\_0PAD }further details are provided in the source code comments. \\
\\
Given the previous parameters the unit shall generate correct RTL without any manual modification to the source code.\\
\\
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\section{Interface}\label{interface}
\label{chapter 4}
Interface signals of the module are listed in the table below.
%TODO
%\begin{table}[H]
% \centering
% \begin{tabular}{lllll}
% \hline
% Port\_Name & Direction & Width & Index & Description \\
% \hline
% CLK & INPUT & 1 & - & Main clock, up to 200MHz \\
% RST & INPUT & 1 & - & Hard reset. Active LOW \\
% SOFT\_RST & INPUT & 1 & - & Soft reset. Active LOW \\
% RESET\_ADDRESS & INPUT & 40 & - & Inital address of PC after soft or hard reset \\
% CSR\_RW\_RDATA & INPUT & 64 & - & - \\
% \end{tabular}
%\end{table}
\section{Reset behavior}
The module contains a single global reset, called \textbf{rstn\_i }it is asynchronous and active low.\\
\\
When reset is active shall any internal register shall be set to 0. Specially the current weight addition (\textbf{ccc\_suma\_int}) and current quota (\textbf{quota\_int})\\
\\Interruption shall become inactive while the unit is in reset or disabled.
\section{What could not happen}
\textbf{DEBUG} and define shall be undefined for synthesis.\\
\\
\textbf{SYNT} shall be defined for synthesis.
\ No newline at end of file
\section{Behavior}\label{behavior}
ext subsections describe the different functional states of the unit and interruption capabilities.
\subsection{Quota update}
The unit requires a synchronization mechanism with the wrapper since the available quota is registered at the top level and internally. Such synchronization is done through an update signal (\textbf{update\_quota\_i}) provided by the module that instances the MCCU. Each quota for each core has an individual update bit. \textbf{If the unit is active and the update bit is active} the interal quota (\textbf{quota\_int}) takes the input quota (quota\_int). Having an external quota that remains constant and an internal quota allows the developers to see the actual quota consumed and the initial quota without having to keep track in software.\\
\\
\subsection{IDLE state}
If MCCU is inactive and the update bit is not active \textbf{(!enable\_i \&\& update\_quota\_i[i])} the internal quota remains the same than in the previous cycle.
\subsection{Active without update}\label{awou}
When the unit is active state and no quota update is required \textbf{(enable\_i \&\& !update\_quota\_i[i])} the internal quota (\textbf{quota\_int}) is set to either the current quota minus the addition of weights of the active events (\textbf{ccc\_suma\_int}) or if an underflow is going to be produced, it is set to 0.
\subsection{Active without update}
If the unit is active but the update bit is set high (\textbf{enable\_i \&\& update\_quota\_i[i]}) the same operation of section \ref{awou} is performed, but instead of subtracting to the last quota, the incoming quota (quota\_i[i]) is used instead.
\subsection{Interruptions}
Interruptions are generated when the unit is enabled and not in reset. Even if the reset is not explicitly guarded, while the unit is in reset the comparison among the current addition of active weights (\textbf{ccc\_suma\_int}) and the internal quota (\textbf{quota\_int}) will not cause an interrupt. If ccc\_suma\_int[i] is larger than quota\_int[i] the interruption will rise for core i.
\subsection{Addition of weights}
The addition of weights is done in two steps, first the event will set if the weight needs to be added or not. To do so an internal signal called \textbf{events\_weights\_int} is used. If the event is active events\_weights\_int will contain the weight forwarded for the value in \textbf{events\_weights\_i} otherwise the value will be 0. events\_weights\_int is always added together in a single cycle and the result is finally stored in \textbf{ccc\_suma\_int}.
\subsection{Packages and structures}
No packages and structures are used in this module.
\section{Special cases, corner cases}
Depending on the number of signals and the size of the weights the addition of events may result in overflow. Is important to ensure that \textbf{ccc\_suma\_int} is wide enough to store the addition of the maximum value of all the weights.\\
\\
The user shall ensure that the update bit is set and released to avoid missing interruptions and allow normal operation og the unit.\\
\\
CC=pdflatex
all: spec
spec: main.tex 1-Section.tex 2-Section.tex 3-Section.tex 4-Section.tex 5-Section.tex 6-Section.tex 7-Section.tex 8-Section.tex
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\huge PMU\_MCCU specification version v1 \\ % The assignment title
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\author{ Guillem Cabo Pitarch} % Your name
\date{\today} % Today's date or a custom date
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......@@ -2,7 +2,9 @@
// ProjectName: PMU research
// Function : Implementation of Maximum-Contention Control Unit (MCCU):
// ResourceAccess Count and Contention Time Enforcement.
// Description: Mechanism assigns
// Description: Mechanism that estimates the contention caused for each event,
// the contention caused is substracted from the asigned quota.
// When the quota is 0 an interrupt is risen.
// Coder : G.Cabo
// References : https://upcommons.upc.edu/handle/2117/133656
......@@ -60,7 +62,7 @@
//avoid width mismatch when add: OVERFLOW_PROT + WEIGHTS_WIDTH
localparam O_W_0PAD = OVERFLOW_PROT-WEIGHTS_WIDTH;
//internal registers
//internal signals
reg [DATA_WIDTH-1:0] quota_int [0:N_CORES-1];//Quota set by external registers
wire [WEIGHTS_WIDTH-1:0] events_weights_int [0:N_CORES-1] [0:CORE_EVENTS-1];
reg [OVERFLOW_PROT-1:0] ccc_suma_int [0:N_CORES-1];//Addition of current cycle
......@@ -73,7 +75,7 @@
integer debug_tmp = 0;
`endif
/*----------
Generate one mechanism to monitor te quota for each of the cores in the
Generate one mechanism to monitor the quota for each of the cores in the
SOC,
----------*/
integer i;
......@@ -244,8 +246,8 @@
end
end
/*----------
Set weights of events, as this module is used whith an
axi-lite wrapper the values are already registered
Set weights of events, as this module is used whith a
wrapper the values are already registered
outside and only need to be forwarded without register them internally.
Apply the event as a mask. If the event is inactive in the current cycle
0 is forwarded in events_weights_int for that event.
......
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