Commit 2b6aff07 authored by GuillemCabo's avatar GuillemCabo
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add GRLIB like documentation for SELENE integration

parent 7c2dc500
\newpage
\section{Overview}
\label{chapter1}
The SafePMU (Safe Performance Monitoring Unit) is an AHB slave capable of monitoring SoC events, enforce contention control, and identifying profiling errors on run-time.
Figure "\ref{fig:blkdia}" shows the structure of the unit. It is composed of an ahb wrapper (\textit{ahb\_wrapper.vhd}) that maps the SystemVerilog implementation into a VHDL module that can be instanced in SELENE and De-RISC SoCs. The SystemVerilog AHB interface (\textit{pmu\_ahb.sv}) offers support for a subset of AHB requests. This module also instances the interface agnostic PMU (\textit{PMU\_raw.sv}). The latter is used as the generator of the statistic unit. It generates the memory map and the instances for each of the features.\\
\\
The main features are:\\
\begin{itemize}
\item \textbf{Self-test:} Allows to configure the counters' inputs to a fixed value bypassing the crossbar and ignoring the inputs. This mode allows for tests of the software and the unit under known conditions.
\item \textbf{Crossbar:} Allows to route any input event to any counter.
\item \textbf{Counters:} Group of simple counters with settable initial values and general control register.
\item \textbf{Overflow:} Detection of overflow for counters, interrupt capable with dedicated interruption vector and per counter interrupt enable.
\item \textbf{Quota:} Deprecated \textit{(It may be excluded in a future release)}
\item \textbf{MCCU }(Maximum Contention Control Unit) : Contention control measures for each core. Interruption capable after a threshold of contention is exceeded. It accepts real contention signals or estimation through weights.
\item \textbf{RDC }(Request Duration Counters): Provides measures of the pulse length of a given input signal (watermark). It can be used to determine maximum latency and cycles of uninterrupted contentions. Each of the counters can trigger an interrupt at a user-defined threshold.
\end{itemize}
The default configuration of this unit supports 4 cores and 32 input signals. In future releases such parameters (VHDL generics) will be exposed to the top level.
\begin{figure}[H]
\includegraphics[keepaspectratio,width=\columnwidth]{img/GRLIB_SU.png}
\caption{Block diagram statistics unit structure}
\label{fig:blkdia}
\end{figure}
This diff is collapsed.
\section{Configuration options}
\label{chapter 4}
Table \ref{generics} shows the configuration parameters exposed by \textit{ahb\_wrapper.vhd}. Given the current development status, changes to the configuration options may require manual modifications to internal modules and software drivers. Future releases will expose parameters to enable individual PMU features and allow for more flexibility.\\
\\
\begin{table}[H]
\caption{Configuration options (VHDL ports)}
\label{generics}
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|}
\hline
\textbf{Generic} & \textbf{Function} & \textbf{Allowed range} & \textbf{Default}\\
\hline
HADDR & AHB base address &0 to 16\#fff\# & 0\\
\hline
HMASK & AHB address mask &0 to 16\#fff\# & 16\#fff\#\\
\hline
N\_REGS & Total of accessible registers & 2 to 64 & 43\\
\hline
PMU\_COUNTERS & Number of generic counters. Same as crossbar outputs& 1 to 32 &24 \\
\hline
N\_SOC\_EV &SoC signals. Inputs to the crossbar& 1 to 64 & 32 \\
\hline
REG\_WIDTH &Size of registers and counters & 32 \textbf{or} 64 & 32 \\
\hline
\end{tabular}
\end{small}
\end{table}
\section{Signal descriptions}
Table \ref{t_ports} shows the interface of the core (VHDL ports).
\begin{table}[H]
\caption{Signal descriptions (VHDL ports)}
\label{t_ports}
\centering
\begin{footnotesize}
\begin{tabular}{|l|l|l|l|l|}
\hline
\textbf{Signal name} & \textbf{Field} & \textbf{Type} & \textbf{Function} & \textbf{Active}\\
\hline
RST & &Input &Reset & Low\\
\hline
CLK & &Input &AHB master bus clock & -\\
\hline
PMU\_EVENTS & &Input & Input for regular SoC events & -\\
\hline
CCS\_CONTENTION & &Input & Input for contention cycle stack signals that measure contention & -\\
\hline
CCS\_LATENCY & &Input & Input for contention cycle stack signals that measure access latency & -\\
\hline
AHBSI & * &Input & AHB slave input signals& -\\
\hline
AHBSO & * &Output &AHB slave output signals, includes interrupts & - \\
\hline
\end{tabular}
\end{footnotesize}
\end{table}
\section{Library dependences}
Table \ref{dep_tab} shows the libraries used when instantiating the core (VHDL libraries).\\
%%TODO: check if the libraries are actually needed
\begin{table}[H]
\caption{Library dependencies}
\label{dep_tab}
\centering
\begin{tabular}{|l|l|l|l|}
\hline
\textbf{Library} & \textbf{Package} & \textbf{Imported units} & \textbf{Description} \\
\hline
IEEE & std\_logic\_1164 & Types & Standard logic types\\
\hline
GRLIB & amba & Signals & AMBA signal definitions\\
\hline
GRLIB & config & Types & Amba P\&P types\\
\hline
GRLIB & devices & Types & Device names and vendors \\
\hline
GRLIB & stdlib & All & Common VHDL functions\\
\hline
GAISLER & noelv & Signals & Counter vectors and types \\
\hline
BSC & pmu\_module & Instances and signals & Instances and signal definitions for the PMU\\
\hline
\end{tabular}
\end{table}
\ No newline at end of file
\section{Instantiation}
An example design is provided in the context of SELENE and De-RISC. Integration examples of earlier releases of the unit along LEON3MP can be provided under demand.\\
\\
\belowcaptionskip=-10pt
\begin{lstlisting}[label=ins-prot,caption=SafePMU instance example for gpp\_sys,style=vhdl]
-- Include BSC library
library bsc;
use bsc.pmu_module.all;
--Provide a non-overlaping hsidx
constant hsidx_pmu : integer := 6;
--Update the hsidx of the next slave
constant nextslv : integer := hsidx_pmu + 1;
--Declare events and signals of interest. They may change
--for each use case. Route such events to pmu_events,
--ccs_contention and ccs_latency ports
--Instance of the unit
PMU_inst : ahb_wrapper
generic map(
ncpu => CFG_NCPU,
hindex => hsidx_pmu,
haddr => 16#801#,
hmask => 16#FFF#
)
port map(
rst => rstn,
clk => clkm,
pmu_events => pmu_events,
ccs_contention => ccs_contention,
ccs_latency => ccs_latency,
ahbsi => ahbsi,
ahbso => ahbso(hsidx_pmu));
\end{lstlisting}
Given the development status of the module and drivers it is recommended to not modify the internal parameters of the module.\\
\end{document}
\section{Special cases, corner cases}
After reset of a top module (PMU\_raw for instance) you may experience that all the outputs route the event in the first position of vector\_i. This is intended behavior and happens due to the reset of the configuration registers (cfg\_i).\\
\\
In the default integration with PMU\_raw.sv there is a self-test capability that bypasses the crossbar with certain test patterns. This \textbf{self-test capability} is configured in the main configuration register of PMU\_raw.sv. Be sure to have this function disabled if you plan to use the crossbar.
\ No newline at end of file
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%----------------------------------------------------------------------------------------
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