Dualcore setup & area synth

include RTL and software changes to run multicore SIMULATIONS with pmu, no FPGA tested. Includes yosys scripts for area calculation

hdl/AXI_PMU.sv

@@ -53,6 +53,9 @@
         input  wire        EV13_i            ,// signal  
         input  wire        EV14_i            ,// signal  
         input  wire        EV15_i            ,// signal  
+        input  wire        EV16_i            ,// signal  
+        input  wire        EV17_i            ,// signal  
+        input  wire        EV18_i            ,// signal  
         
         //outputs
         output wire        int_overflow_o,
@@ -62,13 +65,87 @@
         output wire        int_quota_c0_o,
         output wire        int_quota_c1_o
     );
-    
-    localparam integer N_COUNTERS	= 16;
+    //Different configurations to get are usage
+    `ifdef YOSYS_1
+    localparam integer N_COUNTERS	= 19;
     // Configuration registers
     localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 1;
+    localparam OVERFLOW = 1;
+    localparam QUOTA= 1;
+    localparam MCCU= 1;
+    `elsif YOSYS_2
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 2;
+    localparam OVERFLOW = 1;
+    localparam QUOTA= 1;
+    localparam MCCU= 1;
+    `elsif YOSYS_3
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 3;
+    localparam OVERFLOW = 1;
+    localparam QUOTA= 1;
+    localparam MCCU= 1;
+    `elsif YOSYS_4
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 4;
+    localparam OVERFLOW = 1;
+    localparam QUOTA= 1;
+    localparam MCCU= 1;
+    `elsif YOSYS_5
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 1;
+    localparam OVERFLOW = 0;
+    localparam QUOTA= 0;
+    localparam MCCU= 0;
+    `elsif YOSYS_6
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 1;
+    localparam OVERFLOW = 1;
+    localparam QUOTA= 0;
+    localparam MCCU= 0;
+    `elsif YOSYS_7
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 1;
+    localparam OVERFLOW = 0;
+    localparam QUOTA= 1;
+    localparam MCCU= 0;
+    `elsif YOSYS_8
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 1;
+    localparam OVERFLOW = 0;
+    localparam QUOTA= 0;
+    localparam MCCU= 1;
+    `else
+    localparam integer N_COUNTERS	= 19;
+    // Configuration registers
+    localparam integer N_CONF_REGS	= 5;
+    localparam N_CORES = 2;
+    localparam OVERFLOW = 1;
+    localparam QUOTA= 1;
+    localparam MCCU= 1;
+    `endif
     wire [N_COUNTERS-1:0] events_i;
     // Assign individual signals to packed array 
-    assign events_i= { EV15_i,
+    assign events_i= { 
+                         EV18_i,
+                         EV17_i,
+                         EV16_i,
+                         EV15_i,
                          EV14_i,
                          EV13_i,
                          EV12_i,
@@ -85,7 +162,6 @@
                          EV1_i,
                          EV0_i
                         };
-    localparam N_CORES = 2;
     wire MCCU_int_o [N_CORES-1:0];
     //TODO: MCCU_int_o is not assigned parametrically
         //A pack array will look better. Consider chang it on the MCCU
@@ -99,10 +175,10 @@
         .C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
         .N_COUNTERS(N_COUNTERS),
         .N_CONF_REGS(N_CONF_REGS),
-		.OVERFLOW(1), //No
-		.QUOTA(1), //No
-		.MCCU(1), //Yes
-        .N_CORES(2)
+		.OVERFLOW(OVERFLOW), //No
+		.QUOTA(QUOTA), //No
+		.MCCU(MCCU), //Yes
+        .N_CORES(N_CORES)
     ) inst_AXI_PMU (
         .*
 /*        .S_AXI_ACLK_i(S_AXI_ACLK_i),

submodules/MCCU/hdl/MCCU.sv

@@ -161,7 +161,7 @@
             end else begin
             //if the  unit has been reseted in current or  previous cycle
                 for (i=0; i<N_CORES; i=i+1) begin : AssertionsQuotaReset
-                    assert(quota_int[i] == {DATA_WIDTH{1'b0}});
+                    assert(quota_int[i] == {DATA_WIDTH{1'b1}});
                 end
             end
             `endif

synth/README.md

+How to run synthesis?
+===============
+
+In order to do the synthesis of this module you need installed:
+Yosys ->  http://www.clifford.at/yosys/
+Verific -> http://www.clifford.at/yosys/
+FreePDK45  -> https://www.eda.ncsu.edu/wiki/FreePDK45:Contents#Current_Version
+
+Verific can be obtained for free through the sby package granted to BSC.
+https://symbiyosys.readthedocs.io/en/latest/
+
+All the paths in the .ys files containing the falg -liberty have the absolute 
+path to the liberty files of the pdk that we are using. Since this paths are
+hardcoded you will need to set yours manually. it shall be replaced by a system
+variable in the future.

synth/run_synth.sh

+#Name of the report follows this format
+# Q: Quota on
+# O: Overflow on
+# M: MCCU on
+# NC: Number of counters
+# NCFG: Number configuration registers
+# C: Number of cores
+echo "Starting synth in parallel of  the different test cases"
+echo "This use to take between 1 and 3 minutes"
+echo "Area for FreePDK45 is reported in square micrometers"
+echo "0/8 runs done"
+
+#`ifdef YOSYS_1
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 1;
+#    localparam OVERFLOW = 1;
+#    localparam QUOTA= 1;
+#    localparam MCCU= 1;
+yosys -D YOSYS_1 yosys_45.ys > ./logs/QOM_NC19-NCFG5-C1.log &
+
+#`elsif YOSYS_2
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 2;
+#    localparam OVERFLOW = 1;
+#    localparam QUOTA= 1;
+#    localparam MCCU= 1;
+yosys -D YOSYS_2 yosys_45.ys > ./logs/QOM_NC19-NCFG5-C2.log &
+#`elsif YOSYS_3
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 3;
+#    localparam OVERFLOW = 1;
+#    localparam QUOTA= 1;
+#    localparam MCCU= 1;
+yosys -D YOSYS_3 yosys_45.ys > ./logs/QOM_NC19-NCFG5-C3.log &
+#`elsif YOSYS_4
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 4;
+#    localparam OVERFLOW = 1;
+#    localparam QUOTA= 1;
+#    localparam MCCU= 1;
+yosys -D YOSYS_4 yosys_45.ys > ./logs/QOM_NC19-NCFG5-C4.log
+echo "4/8 runs done"
+#`elsif YOSYS_5
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 1;
+#    localparam OVERFLOW = 0;
+#    localparam QUOTA= 0;
+#    localparam MCCU= 0;
+yosys -D YOSYS_5 yosys_45.ys > ./logs/NC19-NCFG5-C1.log &
+#`elsif YOSYS_6
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 1;
+#    localparam OVERFLOW = 1;
+#    localparam QUOTA= 0;
+#    localparam MCCU= 0;
+yosys -D YOSYS_6 yosys_45.ys > ./logs/O_NC19-NCFG5-C1.log &
+#`elsif YOSYS_7
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 1;
+#    localparam OVERFLOW = 0;
+#    localparam QUOTA= 1;
+#    localparam MCCU= 0;
+yosys -D YOSYS_7 yosys_45.ys > ./logs/Q_NC19-NCFG5-C1.log &
+#`elsif YOSYS_8
+#    localparam integer N_COUNTERS	= 19;
+#    // Configuration registers
+#    localparam integer N_CONF_REGS	= 5;
+#    localparam N_CORES = 1;
+#    localparam OVERFLOW = 0;
+#    localparam QUOTA= 0;
+#    localparam MCCU= 1;
+yosys -D YOSYS_8 yosys_45.ys > ./logs/M_NC19-NCFG5-C1.log
+wait
+echo "8/8 runs done"
+echo "Done! Reporting area & cycle time"
+cd logs
+ack "Chip area for top module "
+ack "Delay "
+cd ..

synth/synth.constr

+set_driving_cell INVX1 
+set_load 0.015
+

synth/yosys_45.ys

+#read file
+verific -sv ../hdl/AXI_PMU.sv
+verific -sv ../hdl/AXI_PMU_interface_v1_0_S00_AXI.sv
+verific -sv ../submodules/MCCU/hdl/MCCU.sv
+verific -import AXI_PMU
+prep -top AXI_PMU
+
+#high-level
+proc; opt; fsm; opt; memory; opt
+
+#internal cell library
+techmap; opt
+
+
+#mapping flip-flops to mycells.lib
+#TODO: Replace absolute path libraries by a variable
+dfflibmap -liberty /home/bscuser/PDK_opensource/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/osu_soc/lib/files/gscl45nm.lib
+
+#mapping logic to mycells.lib
+#abc -liberty mycells.lib
+#TODO: Replace absolute path libraries by a variable
+abc -D 10  -constr synth.constr -liberty /home/bscuser/PDK_opensource/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/osu_soc/lib/files/gscl45nm.lib
+#get area
+#TODO: Replace absolute path libraries by a variable
+stat -liberty /home/bscuser/PDK_opensource/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/osu_soc/lib/files/gscl45nm.lib
+
+#cleanup
+clean
+
+#write synthsized design
+write_verilog synth.v

tb/questa_sim/tb_AXI_PMU.sv

@@ -94,6 +94,9 @@ module tb_AXI_PMU();
     reg     tb_EV13_i;
     reg     tb_EV14_i;
     reg     tb_EV15_i;
+    reg     tb_EV16_i;
+    reg     tb_EV17_i;
+    reg     tb_EV18_i;
     wire    int_overflow_o;
     wire    int_quota_o;
     wire    int_quota_c0_o;
@@ -186,6 +189,9 @@ module tb_AXI_PMU();
         .EV13_i            (tb_EV13_i),   
         .EV14_i            (tb_EV14_i),   
         .EV15_i            (tb_EV15_i),   
+        .EV16_i            (tb_EV16_i),   
+        .EV17_i            (tb_EV17_i),   
+        .EV18_i            (tb_EV18_i),   
         .int_overflow_o (int_overflow_o),
         .int_quota_o(int_quota_o),
         .int_quota_c0_o(int_quota_c0_o),
@@ -555,8 +561,10 @@ task automatic init_sim;
                 );
                 value = tb_r_data;
                 if (up2!=dut_AXI_PMU.inst_AXI_PMU.slv_reg[r_addr>>2]) begin
+                    `START_RED_PRINT
                     $error("FAIL all_counters. Register %d has captured %h \
                     events instead of expected %h", r_addr>2,dut_AXI_PMU.inst_AXI_PMU.slv_reg[r_addr>>2], up2);
+                    `END_COLOR_PRINT
                     tmp=1;
                 end
             end
@@ -580,19 +588,21 @@ task automatic init_sim;
                     .delay(4)
             );
             value = tb_r_data;
-            up2 ='hffff;
+            up2 ='h7ffff;// Depends on the nº of counters
             if (dut_AXI_PMU.inst_AXI_PMU.slv_reg[base_overflow>>2]!=up2) begin
+                `START_RED_PRINT
                 $error("FAIL all_counters. Overflow register %d has captured %h \
                     interrupts instead of expected %h", base_overflow>2
                     ,dut_AXI_PMU.inst_AXI_PMU.slv_reg[base_overflow>>2], up2);
+                `END_COLOR_PRINT
                 tmp=1;
             end
             if(int_overflow_o != 1'b1)
                 $error("Overflow Interrupt has not been risen");
         if(tmp==0)
         `START_GREEN_PRINT
-            $display("PASS overflow_counters.");
-            $display("PASS all_counters.");
+        $display("PASS overflow_counters.");
+        $display("PASS all_counters.");
         `END_COLOR_PRINT
         end
         
@@ -616,6 +626,9 @@ task automatic init_sim;
         tb_EV13_i=1;
         tb_EV14_i=1;
         tb_EV15_i=1;
+        tb_EV16_i=1;
+        tb_EV17_i=1;
+        tb_EV18_i=1;
         end
     endtask 
 
@@ -638,6 +651,9 @@ task automatic init_sim;
             tb_EV13_i=0;
             tb_EV14_i=0;
             tb_EV15_i=0;
+            tb_EV16_i=0;
+            tb_EV17_i=0;
+            tb_EV18_i=0;
         end
     endtask
 

tb/questa_sim/wave.do

@@ -55,8 +55,35 @@ add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/generate_MCCU/inst_MCCU/
 add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/generate_MCCU/inst_MCCU/WEIGHTS_WIDTH
 add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/generate_MCCU/MCCU_events_weights_int
 add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/generate_MCCU/weights_flat_bitarray
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/C_S_AXI_DATA_WIDTH
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/C_S_AXI_ADDR_WIDTH
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/N_COUNTERS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/N_CONF_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/OVERFLOW
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/QUOTA
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/N_CORES
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/ADDR_LSB
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/OPT_MEM_ADDR_BITS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/N_OVERFLOW_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/N_QUOTA_MASK
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/N_QUOTA_LIMIT
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/BASE_QUOTA
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/BASE_MCCU
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_DATA_WIDTH
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_WEIGHTS_WIDTH
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_N_CORES
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_CORE_EVENTS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_WEIGHTS_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_R_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/MCCU_RW_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/BASE_MCCU_R_ONLY
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/R_ONLY_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/RW_REGS
+add wave -noupdate /tb_AXI_PMU/dut_AXI_PMU/inst_AXI_PMU/TOTAL_REGS
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1766058 ps} 0}
+WaveRestoreCursors {{Cursor 1} {1764651 ps} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 506
 configure wave -valuecolwidth 241

tb/software_tests/multicore_pmu_qsort/.gitignore

+*~
+*.riscv
+*.host
+*.o
+*.dump
+*.out
+*.hex
+.*.swp
+autom4te.cache

tb/software_tests/multicore_pmu_qsort/Makefile.in

+prefix          := @prefix@
+abs_top_src_dir := @abs_top_srcdir@
+instbasedir     := $(DESTDIR)$(prefix)
+bmarkdir        := $(abs_top_src_dir)/programs
+isa_src_dir     := $(abs_top_src_dir)/isa
+
+all: programs isa
+
+install: all
+	install -p -m 644 *.hex $(instbasedir)/share/riscv-tests
+
+programs:
+	$(MAKE) -f $(bmarkdir)/Makefile bmarkdir=$(bmarkdir)
+
+isa:
+	$(MAKE) -f $(isa_src_dir)/Makefile isa_src_dir=$(isa_src_dir)
+
+.PHONY: programs isa

tb/software_tests/multicore_pmu_qsort/configure.ac

+AC_INIT(riscv-tests, 1.0)
+
+cross_compiling=yes
+AC_PROG_CC([riscv64-unknown-elf-gcc])
+
+AC_OUTPUT(
+    Makefile
+)

tb/software_tests/multicore_pmu_qsort/env/LICENSE

+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

tb/software_tests/multicore_pmu_qsort/env/p/link.ld

+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x100;
+  .text.init : { *(.text.init) }
+  .text : { *(.text) }
+  .data ALIGN(0x1000) : { *(.data) }
+  .bss : { *(.bss) }
+  _end = .;
+}
+

tb/software_tests/multicore_pmu_qsort/env/pm/link.ld

+../p/link.ld
\ No newline at end of file

tb/software_tests/multicore_pmu_qsort/env/pm/riscv_test.h

+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_MULTI_CORE_H
+#define _ENV_PHYSICAL_MULTI_CORE_H
+
+#include "../p/riscv_test.h"
+
+#undef RISCV_MULTICORE_DISABLE
+#define RISCV_MULTICORE_DISABLE
+
+#endif

tb/software_tests/multicore_pmu_qsort/env/pt/link.ld

+../p/link.ld
\ No newline at end of file

tb/software_tests/multicore_pmu_qsort/env/pt/riscv_test.h

+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
+#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
+
+#include "../p/riscv_test.h"
+
+#define TIMER_INTERVAL 2
+
+#undef EXTRA_TVEC_USER
+#define EXTRA_TVEC_USER                                                 \
+        csrw mscratch, a0;                                              \
+        csrr a0, mcause;                                                \
+        bltz a0, _interrupt_handler;                                    \
+_skip:                                                                  \
+
+#undef EXTRA_INIT_TIMER
+#define EXTRA_INIT_TIMER                                                \
+        ENABLE_TIMER_INTERRUPT;                                         \
+        j _jump_around_interrupt_handler;                               \
+        INTERRUPT_HANDLER;                                              \
+_jump_around_interrupt_handler:                                         \
+
+#define ENABLE_TIMER_INTERRUPT                                          \
+        li a0, MIP_MTIP;                                                \
+        csrs mie, a0;                                                   \
+        csrr a0, mtime;                                                 \
+        addi a0, a0, TIMER_INTERVAL;                                    \
+        csrw mtimecmp, a0;                                              \
+
+#if SSTATUS_XS != 0xc000
+# error
+#endif
+#define XS_SHIFT 14
+
+#define INTERRUPT_HANDLER                                               \
+_interrupt_handler:                                                     \
+        slli a0, a0, 1;                                                 \
+        srli a0, a0, 1;                                                 \
+        add a0, a0, -IRQ_TIMER;                                         \
+        bnez a0, _skip;                                                 \
+        csrr a0, mtime;                                                 \
+        addi a0, a0, TIMER_INTERVAL;                                    \
+        csrw mtimecmp, a0;                                              \
+        csrr a0, mscratch;                                              \
+        eret;                                                           \
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#undef EXTRA_DATA
+#define EXTRA_DATA                                                      \
+        .align 3;                                                       \
+regspill:                                                               \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+evac:                                                                   \
+        .skip 32768;                                                    \
+
+#endif