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CAOS_HW
HDL_IP
SafeSU
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65e97117250dcef76dfafae58cf476791b8669f0
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bsc_pmu
tb
questa_sim
axi_test_master
docs
axi_test_master.odt
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WIP: Doing unit tests
· 65e97117
Guillem
authored
Sep 04, 2019
For the TB an AXI-LITE master from verilog.pro has been added
65e97117
