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 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite -- Symbiotic EDA Edition [20190521A ] |
 |                                                                            |
 |  Copyright (C) 2012 - 2019 Symbiotic GmbH                                  |
 |                                                                            |
 |  Licensed to: Symbiotic EDA Eval License Program                           |
 |  Licensee contact: office@symbioticeda.com                                 |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.8+472 (git sha1 c907899, clang 3.8.0-2ubuntu4 -fPIC -Os)

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-- Running command `read -define D16' --

1. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.

-- Executing script file `yosys_45.ys' --

2. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'instances.sv'

3. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
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VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/triple_reg.sv'
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4. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
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VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/sbf_reg.sv'
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5. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
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VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/ham_reg.sv'
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6. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/reg_sbf.sv'

7. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/way3_voter.sv'

8. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/hamming16t11d_enc.sv'

9. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/hamming16t11d_dec.sv'

10. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/com_tr.sv'

11. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May  1 16:05:25 2019.
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Adding Verilog module 'instances' to elaboration queue.
Running hier_tree::Elaborate().
VERIFIC-INFO [VERI-1018] instances.sv:20: compiling module 'instances'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/com_tr.sv:21: compiling module 'com_tr(IN_WIDTH=16)'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/triple_reg.sv:16: compiling module 'triple_reg(IN_WIDTH=16)'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/way3_voter.sv:24: compiling module 'way3_voter(IN_WIDTH=16)'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/sbf_reg.sv:16: compiling module 'sbf_reg(IN_WIDTH=16)'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/reg_sbf.sv:26: compiling module 'reg_sbf(IN_WIDTH=16)'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/ham_reg.sv:16: compiling module 'ham_reg'
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VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_enc.sv:18: compiling module 'hamming16t11d_enc'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/hamming16t11d_dec.sv:18: compiling module 'hamming16t11d_dec'
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Importing module instances.
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Importing module com_tr(IN_WIDTH=16).
Importing module triple_reg(IN_WIDTH=16).
Importing module sbf_reg(IN_WIDTH=16).
Importing module ham_reg.
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Importing module way3_voter(IN_WIDTH=16).
Importing module reg_sbf(IN_WIDTH=16).
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Importing module hamming16t11d_enc.
Importing module hamming16t11d_dec.
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12. Executing PREP pass.
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12.1. Executing HIERARCHY pass (managing design hierarchy).
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12.1.1. Analyzing design hierarchy..
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Top module:  \instances
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Used module:     \ham_reg
Used module:         \hamming16t11d_dec
Used module:         \hamming16t11d_enc
Used module:     \sbf_reg(IN_WIDTH=16)
Used module:         \reg_sbf(IN_WIDTH=16)
Used module:     \triple_reg(IN_WIDTH=16)
Used module:         \way3_voter(IN_WIDTH=16)
Used module:     \com_tr(IN_WIDTH=16)

12.1.2. Analyzing design hierarchy..
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Top module:  \instances
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Used module:     \ham_reg
Used module:         \hamming16t11d_dec
Used module:         \hamming16t11d_enc
Used module:     \sbf_reg(IN_WIDTH=16)
Used module:         \reg_sbf(IN_WIDTH=16)
Used module:     \triple_reg(IN_WIDTH=16)
Used module:         \way3_voter(IN_WIDTH=16)
Used module:     \com_tr(IN_WIDTH=16)
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Removed 0 unused modules.

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12.2. Executing PROC pass (convert processes to netlists).
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12.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.

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12.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.

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12.2.3. Executing PROC_INIT pass (extract init attributes).
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12.2.4. Executing PROC_ARST pass (detect async resets in processes).
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12.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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12.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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12.2.7. Executing PROC_DFF pass (convert process syncs to FFs).
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12.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.

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12.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module hamming16t11d_dec.
<suppressed ~1 debug messages>
Optimizing module hamming16t11d_enc.
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Optimizing module reg_sbf(IN_WIDTH=16).
<suppressed ~1 debug messages>
Optimizing module way3_voter(IN_WIDTH=16).
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Optimizing module ham_reg.
Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module instances.
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12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..
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Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
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Finding unused cells or wires in module \instances..
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Removed 1 unused cells and 267 unused wires.
<suppressed ~22 debug messages>
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12.5. Executing CHECK pass (checking for obvious problems).
checking module com_tr(IN_WIDTH=16)..
checking module ham_reg..
checking module hamming16t11d_dec..
checking module hamming16t11d_enc..
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checking module instances..
checking module reg_sbf(IN_WIDTH=16)..
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checking module sbf_reg(IN_WIDTH=16)..
checking module triple_reg(IN_WIDTH=16)..
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checking module way3_voter(IN_WIDTH=16)..
found and reported 0 problems.

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12.6. Executing OPT pass (performing simple optimizations).
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12.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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12.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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<suppressed ~6 debug messages>
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
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Removed a total of 2 cells.
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12.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \instances..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
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<suppressed ~20 debug messages>
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12.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
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    New input vector for $reduce_or cell $verific$reduce_or_12$../../submodules/seu_ip/com_tr.sv:62$109: { $verific$n76$103 [0] $verific$n76$103 [1] $verific$n76$103 [2] $verific$n76$103 [3] $verific$n76$103 [4] $verific$n76$103 [5] $verific$n76$103 [6] $verific$n76$103 [7] $verific$n76$103 [8] $verific$n76$103 [9] $verific$n76$103 [10] $verific$n76$103 [11] $verific$n76$103 [12] $verific$n76$103 [13] $verific$n76$103 [14] $verific$n76$103 [15] }
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  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 1 changes.

12.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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12.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

12.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

12.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
Optimizing module way3_voter(IN_WIDTH=16).

12.6.9. Rerunning OPT passes. (Maybe there is more to do..)

12.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \instances..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
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Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
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Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
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<suppressed ~20 debug messages>
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12.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
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  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
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  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
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  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 0 changes.

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12.6.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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12.6.13. Executing OPT_RMDFF pass (remove dff with constant values).
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12.6.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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12.6.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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12.6.16. Finished OPT passes. (There is nothing left to do.)
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12.7. Executing WREDUCE pass (reducing word size of cells).
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Removed top 2 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_11$../../submodules/seu_ip/hamming16t11d_dec.sv:45$376 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_14$../../submodules/seu_ip/hamming16t11d_dec.sv:46$379 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_17$../../submodules/seu_ip/hamming16t11d_dec.sv:47$382 ($eq).
Removed top 1 bits (of 4) from port A of cell hamming16t11d_dec.$verific$equal_20$../../submodules/seu_ip/hamming16t11d_dec.sv:48$385 ($eq).
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12.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
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12.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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12.10. Executing MEMORY_COLLECT pass (generating $mem cells).
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12.11. Executing OPT pass (performing simple optimizations).
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12.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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12.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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12.11.3. Executing OPT_RMDFF pass (remove dff with constant values).
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12.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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12.11.5. Finished fast OPT passes.

12.12. Printing statistics.

=== com_tr(IN_WIDTH=16) ===

   Number of wires:                 10
   Number of wire bits:             85
   Number of public wires:           8
   Number of public wire bits:      53
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $dff                            3
     $mux                            1
     $reduce_or                      1
     $xor                            1

=== ham_reg ===

   Number of wires:                 11
   Number of wire bits:            101
   Number of public wires:          10
   Number of public wire bits:      85
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     $dff                            1
     $mux                            1
     hamming16t11d_dec               1
     hamming16t11d_enc               1

=== hamming16t11d_dec ===
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   Number of wires:                 29
   Number of wire bits:             57
   Number of public wires:           4
   Number of public wire bits:      32
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 41
     $and                            1
     $eq                            11
     $mux                           11
     $not                           12
     $reduce_bool                    1
     $reduce_xor                     5

=== hamming16t11d_enc ===

   Number of wires:                  4
   Number of wire bits:             32
   Number of public wires:           4
   Number of public wire bits:      32
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  5
     $reduce_xor                     5
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=== instances ===

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   Number of wires:                 11
   Number of wire bits:             51
   Number of public wires:          11
   Number of public wire bits:      51
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   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
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   Number of cells:                  4
     com_tr(IN_WIDTH=16)             1
     ham_reg                         1
     sbf_reg(IN_WIDTH=16)            1
     triple_reg(IN_WIDTH=16)         1
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=== reg_sbf(IN_WIDTH=16) ===

   Number of wires:                 10
   Number of wire bits:             40
   Number of public wires:           8
   Number of public wire bits:      38
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $dff                            1
     $mux                            2
     $reduce_xor                     2
     $xor                            1

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=== sbf_reg(IN_WIDTH=16) ===

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   Number of wires:                  9
   Number of wire bits:             84
   Number of public wires:           8
   Number of public wire bits:      68
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   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  3
     $dff                            1
     $mux                            1
     reg_sbf(IN_WIDTH=16)            1

=== triple_reg(IN_WIDTH=16) ===

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   Number of wires:                 17
   Number of wire bits:            182
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   Number of public wires:          16
   Number of public wire bits:     166
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
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   Number of cells:                  3
     $dff                            1
     $mux                            1
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     way3_voter(IN_WIDTH=16)         1

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=== way3_voter(IN_WIDTH=16) ===

   Number of wires:                 14
   Number of wire bits:            104
   Number of public wires:           6
   Number of public wire bits:      66
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $eq                             3
     $mux                            6
     $ne                             1
     $not                            1

=== design hierarchy ===

   instances                         1
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     com_tr(IN_WIDTH=16)             1
     ham_reg                         1
       hamming16t11d_dec             1
       hamming16t11d_enc             1
     sbf_reg(IN_WIDTH=16)            1
       reg_sbf(IN_WIDTH=16)          1
     triple_reg(IN_WIDTH=16)         1
       way3_voter(IN_WIDTH=16)       1

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   Number of wires:                115
   Number of wire bits:            736
   Number of public wires:          75
   Number of public wire bits:     591
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   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
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   Number of cells:                 75
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     $and                            1
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     $dff                            7
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     $eq                            14
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     $mux                           23
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     $ne                             1
     $not                           13
     $reduce_bool                    1
     $reduce_or                      1
     $reduce_xor                    12
     $xor                            2

12.13. Executing CHECK pass (checking for obvious problems).
checking module com_tr(IN_WIDTH=16)..
checking module ham_reg..
checking module hamming16t11d_dec..
checking module hamming16t11d_enc..
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checking module instances..
checking module reg_sbf(IN_WIDTH=16)..
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checking module sbf_reg(IN_WIDTH=16)..
checking module triple_reg(IN_WIDTH=16)..
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checking module way3_voter(IN_WIDTH=16)..
found and reported 0 problems.

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13. Executing PROC pass (convert processes to netlists).
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13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.

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13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.

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13.3. Executing PROC_INIT pass (extract init attributes).
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13.4. Executing PROC_ARST pass (detect async resets in processes).
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13.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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13.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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13.7. Executing PROC_DFF pass (convert process syncs to FFs).
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13.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.

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14. Executing OPT pass (performing simple optimizations).
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14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \instances..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
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14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 0 changes.

14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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14.6. Executing OPT_RMDFF pass (remove dff with constant values).

14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
Optimizing module way3_voter(IN_WIDTH=16).

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14.9. Finished OPT passes. (There is nothing left to do.)
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15. Executing FSM pass (extract and optimize FSM).
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15.1. Executing FSM_DETECT pass (finding FSMs in design).
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15.2. Executing FSM_EXTRACT pass (extracting FSM from design).
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15.3. Executing FSM_OPT pass (simple optimizations of FSMs).
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15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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15.5. Executing FSM_OPT pass (simple optimizations of FSMs).
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15.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
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15.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
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15.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
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16. Executing OPT pass (performing simple optimizations).
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16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \instances..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
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Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
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Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
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16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
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  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
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  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
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  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 0 changes.

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16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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16.6. Executing OPT_RMDFF pass (remove dff with constant values).
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16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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16.9. Finished OPT passes. (There is nothing left to do.)
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17. Executing MEMORY pass.
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17.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
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17.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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17.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
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17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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17.5. Executing MEMORY_COLLECT pass (generating $mem cells).
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17.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
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18. Executing OPT pass (performing simple optimizations).
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18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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18.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \instances..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
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Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
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Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
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<suppressed ~20 debug messages>
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18.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
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  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
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  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
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  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 0 changes.

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18.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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18.6. Executing OPT_RMDFF pass (remove dff with constant values).
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18.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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18.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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18.9. Finished OPT passes. (There is nothing left to do.)
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19. Executing TECHMAP pass (map to technology primitives).
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19.1. Executing Verilog-2005 frontend: <techmap.v>
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Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

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19.2. Continuing TECHMAP pass.
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Using extmapper simplemap for cells of type $mux.
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Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $reduce_or.
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Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_xor.
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Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $reduce_bool.
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No more expansions possible.
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<suppressed ~75 debug messages>
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20. Executing OPT pass (performing simple optimizations).
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20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
<suppressed ~27 debug messages>
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
<suppressed ~1 debug messages>
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).
<suppressed ~52 debug messages>

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20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
<suppressed ~171 debug messages>
Finding identical cells in module `\hamming16t11d_enc'.
<suppressed ~18 debug messages>
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
<suppressed ~93 debug messages>
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Removed a total of 94 cells.
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20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \instances..
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  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

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20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
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  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
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  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
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  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 0 changes.

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20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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20.6. Executing OPT_RMDFF pass (remove dff with constant values).
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20.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..
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Removed 14 unused cells and 67 unused wires.
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<suppressed ~19 debug messages>

20.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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20.9. Rerunning OPT passes. (Maybe there is more to do..)
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20.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \com_tr(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \ham_reg..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \hamming16t11d_dec..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \hamming16t11d_enc..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \instances..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \sbf_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \triple_reg(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
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Running muxtree optimizer on module \way3_voter(IN_WIDTH=16)..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

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20.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \com_tr(IN_WIDTH=16).
  Optimizing cells in module \ham_reg.
  Optimizing cells in module \hamming16t11d_dec.
  Optimizing cells in module \hamming16t11d_enc.
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  Optimizing cells in module \instances.
  Optimizing cells in module \reg_sbf(IN_WIDTH=16).
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  Optimizing cells in module \sbf_reg(IN_WIDTH=16).
  Optimizing cells in module \triple_reg(IN_WIDTH=16).
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  Optimizing cells in module \way3_voter(IN_WIDTH=16).
Performed a total of 0 changes.

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20.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\com_tr(IN_WIDTH=16)'.
Finding identical cells in module `\ham_reg'.
Finding identical cells in module `\hamming16t11d_dec'.
Finding identical cells in module `\hamming16t11d_enc'.
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Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=16)'.
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Finding identical cells in module `\sbf_reg(IN_WIDTH=16)'.
Finding identical cells in module `\triple_reg(IN_WIDTH=16)'.
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Finding identical cells in module `\way3_voter(IN_WIDTH=16)'.
Removed a total of 0 cells.

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20.13. Executing OPT_RMDFF pass (remove dff with constant values).
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20.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \com_tr(IN_WIDTH=16)..
Finding unused cells or wires in module \ham_reg..
Finding unused cells or wires in module \hamming16t11d_dec..
Finding unused cells or wires in module \hamming16t11d_enc..
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Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=16)..
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Finding unused cells or wires in module \sbf_reg(IN_WIDTH=16)..
Finding unused cells or wires in module \triple_reg(IN_WIDTH=16)..
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Finding unused cells or wires in module \way3_voter(IN_WIDTH=16)..

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20.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module com_tr(IN_WIDTH=16).
Optimizing module ham_reg.
Optimizing module hamming16t11d_dec.
Optimizing module hamming16t11d_enc.
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Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=16).
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Optimizing module sbf_reg(IN_WIDTH=16).
Optimizing module triple_reg(IN_WIDTH=16).
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Optimizing module way3_voter(IN_WIDTH=16).

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20.16. Finished OPT passes. (There is nothing left to do.)
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21. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
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  cell DFFNEGX1 (noninv, pins=3, area=7.98) is a direct match for cell type $_DFF_N_.
  cell DFFPOSX1 (noninv, pins=3, area=7.98) is a direct match for cell type $_DFF_P_.
  cell DFFSR (noninv, pins=5, area=10.32) is a direct match for cell type $_DFFSR_PNN_.
  create mapping for $_DFFSR_PPN_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFFSR_PNP_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFFSR_PPP_ from mapping for $_DFFSR_PNP_.
  create mapping for $_DFFSR_NNN_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFFSR_NPN_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFFSR_NNP_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFFSR_NPP_ from mapping for $_DFFSR_NNP_.
  create mapping for $_DFF_NN0_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFF_NN1_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFF_NP0_ from mapping for $_DFFSR_NPP_.
  create mapping for $_DFF_NP1_ from mapping for $_DFFSR_NPP_.
  create mapping for $_DFF_PN0_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFF_PN1_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFF_PP0_ from mapping for $_DFFSR_PPP_.
  create mapping for $_DFF_PP1_ from mapping for $_DFFSR_PPP_.
  final dff cell mappings:
    DFFNEGX1 _DFF_N_ (.CLK( C), .D( D), .Q( Q));
    DFFPOSX1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    DFFSR _DFF_NN0_ (.CLK(~C), .D( D), .Q( Q), .R( R), .S( 1));
    DFFSR _DFF_NN1_ (.CLK(~C), .D( D), .Q( Q), .R( 1), .S( R));
    DFFSR _DFF_NP0_ (.CLK(~C), .D( D), .Q( Q), .R(~R), .S( 1));
    DFFSR _DFF_NP1_ (.CLK(~C), .D( D), .Q( Q), .R( 1), .S(~R));
    DFFSR _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .R( R), .S( 1));
    DFFSR _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .R( 1), .S( R));
    DFFSR _DFF_PP0_ (.CLK( C), .D( D), .Q( Q), .R(~R), .S( 1));
    DFFSR _DFF_PP1_ (.CLK( C), .D( D), .Q( Q), .R( 1), .S(~R));
    DFFSR _DFFSR_NNN_ (.CLK(~C), .D( D), .Q( Q), .R( R), .S( S));
    DFFSR _DFFSR_NNP_ (.CLK(~C), .D( D), .Q( Q), .R(~R), .S( S));
    DFFSR _DFFSR_NPN_ (.CLK(~C), .D( D), .Q( Q), .R( R), .S(~S));
    DFFSR _DFFSR_NPP_ (.CLK(~C), .D( D), .Q( Q), .R(~R), .S(~S));
    DFFSR _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .R( R), .S( S));
    DFFSR _DFFSR_PNP_ (.CLK( C), .D( D), .Q( Q), .R(~R), .S( S));
    DFFSR _DFFSR_PPN_ (.CLK( C), .D( D), .Q( Q), .R( R), .S(~S));
    DFFSR _DFFSR_PPP_ (.CLK( C), .D( D), .Q( Q), .R(~R), .S(~S));
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Mapping DFF cells in module `\com_tr(IN_WIDTH=16)':
  mapped 33 $_DFF_P_ cells to \DFFPOSX1 cells.
Mapping DFF cells in module `\ham_reg':
  mapped 16 $_DFF_P_ cells to \DFFPOSX1 cells.
Mapping DFF cells in module `\hamming16t11d_dec':
Mapping DFF cells in module `\hamming16t11d_enc':
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Mapping DFF cells in module `\instances':
Mapping DFF cells in module `\reg_sbf(IN_WIDTH=16)':
  mapped 1 $_DFF_P_ cells to \DFFPOSX1 cells.
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Mapping DFF cells in module `\sbf_reg(IN_WIDTH=16)':
  mapped 16 $_DFF_P_ cells to \DFFPOSX1 cells.
Mapping DFF cells in module `\triple_reg(IN_WIDTH=16)':
  mapped 16 $_DFF_P_ cells to \DFFPOSX1 cells.
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Mapping DFF cells in module `\way3_voter(IN_WIDTH=16)':

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22. Executing ABC pass (technology mapping using ABC).

22.1. Extracting gate netlist of module `\com_tr(IN_WIDTH=16)' to `<abc-temp-dir>/input.blif'..
Extracted 47 gates and 97 wires to a netlist network with 49 inputs and 17 outputs.

22.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Library "gscl45nm" from "/home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib" has 25 cells (6 skipped: 4 seq; 2 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.36 MB. Time =     0.00 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
ABC: + read_constr -v /home/gcabo/BSC/bsc_pmu/synth/FT-resource-comp/synth.constr 
ABC: Setting driving cell to be "INVX1".
ABC: Setting output load to be 0.015000.
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime -D 10 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 10 
ABC: + &put 
ABC: + buffer 
ABC: + upsize -D 10 
ABC: + dnsize -D 10 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =     45 (  6.7 %)   Cap =  3.2 ff ( 18.9 %)   Area =      141.26 ( 62.2 %)   Delay =   184.60 ps  ( 22.2 %)               
ABC: Path  0 --      45 : 0    1 pi      A =   0.00  Df =  10.3   -2.0 ps  S =  20.8 ps  Cin =  0.0 ff  Cout =   5.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --      73 : 2    1 XNOR2X1 A =   4.69  Df =  59.0  -17.1 ps  S =  37.2 ps  Cin =  5.1 ff  Cout =   1.9 ff  Cmax = 228.3 ff  G =   36  
ABC: Path  2 --      74 : 2    1 AND2X2  A =   2.82  Df =  93.7  -12.5 ps  S =  11.7 ps  Cin =  1.8 ff  Cout =   3.0 ff  Cmax = 505.1 ff  G =  159  
ABC: Path  3 --      75 : 3    1 NAND3X1 A =   2.35  Df = 111.0   -5.4 ps  S =  40.6 ps  Cin =  2.7 ff  Cout =   3.0 ff  Cmax =   0.0 ff  G =  113  
ABC: Path  4 --      82 : 3    1 NOR3X1  A =   2.82  Df = 156.9   -3.3 ps  S =  53.3 ps  Cin =  3.1 ff  Cout =   2.8 ff  Cmax =  96.9 ff  G =   87  
ABC: Path  5 --      93 : 3    1 NAND3X1 A =   2.35  Df = 184.6   -7.9 ps  S =  26.2 ps  Cin =  2.7 ff  Cout =   0.0 ff  Cmax =   0.0 ff  G =    0  
ABC: Start-point = pi44 (\reg2 [13]).  End-point = po0 (\error_int).
ABC: + write_blif <abc-temp-dir>/output.blif 

22.1.2. Re-integrating ABC results.
ABC RESULTS:            AND2X1 cells:       17
ABC RESULTS:            AND2X2 cells:        1
ABC RESULTS:           AOI21X1 cells:        1
ABC RESULTS:             BUFX2 cells:        2
ABC RESULTS:             INVX1 cells:        1
ABC RESULTS:           NAND2X1 cells:        2
ABC RESULTS:           NAND3X1 cells:        3
ABC RESULTS:            NOR3X1 cells:        2
ABC RESULTS:           OAI21X1 cells:        1
ABC RESULTS:           XNOR2X1 cells:       13
ABC RESULTS:            XOR2X1 cells:        2
ABC RESULTS:        internal signals:       31
ABC RESULTS:           input signals:       49
ABC RESULTS:          output signals:       17
Removing temp directory.

22.2. Extracting gate netlist of module `\ham_reg' to `<abc-temp-dir>/input.blif'..
Extracted 16 gates and 34 wires to a netlist network with 17 inputs and 16 outputs.

22.2.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Library "gscl45nm" from "/home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib" has 25 cells (6 skipped: 4 seq; 2 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.36 MB. Time =     0.00 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
ABC: + read_constr -v /home/gcabo/BSC/bsc_pmu/synth/FT-resource-comp/synth.constr 
ABC: Setting driving cell to be "INVX1".
ABC: Setting output load to be 0.015000.
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime -D 10 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 10 
ABC: + &put 
ABC: + buffer 
ABC: + upsize -D 10 
ABC: + dnsize -D 10 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =     18 ( 11.1 %)   Cap =  2.1 ff ( 45.6 %)   Area =       42.71 (  5.6 %)   Delay =   126.61 ps  ( 66.7 %)               
ABC: Path  0 --       2 : 0    1 pi     A =   0.00  Df =   3.1   -3.1 ps  S =  10.3 ps  Cin =  0.0 ff  Cout =   1.5 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --      34 : 1    7 BUFX2  A =   2.35  Df =  56.4   -7.1 ps  S =  42.3 ps  Cin =  1.5 ff  Cout =  17.8 ff  Cmax = 518.7 ff  G = 1078  
ABC: Path  2 --      36 : 1   10 BUFX4  A =   2.82  Df =  99.6   -7.7 ps  S =  32.7 ps  Cin =  3.9 ff  Cout =  22.9 ff  Cmax = 999.3 ff  G =  531  
ABC: Path  3 --      37 : 2    1 AND2X1 A =   2.35  Df = 126.6  -11.2 ps  S =  23.7 ps  Cin =  2.1 ff  Cout =   0.0 ff  Cmax = 137.4 ff  G =    0  
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ABC: Start-point = pi1 (\rstn_i).  End-point = po1 ($verific$n22$234 [2]).
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ABC: + write_blif <abc-temp-dir>/output.blif 

22.2.2. Re-integrating ABC results.
ABC RESULTS:            AND2X1 cells:       16
ABC RESULTS:             BUFX2 cells:        1
ABC RESULTS:             BUFX4 cells:        1
ABC RESULTS:        internal signals:        1
ABC RESULTS:           input signals:       17
ABC RESULTS:          output signals:       16
Removing temp directory.

22.3. Extracting gate netlist of module `\hamming16t11d_dec' to `<abc-temp-dir>/input.blif'..
Extracted 74 gates and 91 wires to a netlist network with 16 inputs and 12 outputs.

22.3.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Library "gscl45nm" from "/home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib" has 25 cells (6 skipped: 4 seq; 2 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.36 MB. Time =     0.00 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
ABC: + read_constr -v /home/gcabo/BSC/bsc_pmu/synth/FT-resource-comp/synth.constr 
ABC: Setting driving cell to be "INVX1".
ABC: Setting output load to be 0.015000.
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime -D 10 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 10 
ABC: + &put 
ABC: + buffer 
ABC: + upsize -D 10 
ABC: + dnsize -D 10 
ABC: + stime -p 
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ABC: WireLoad = "none"  Gates =     67 ( 10.4 %)   Cap =  6.1 ff (  3.3 %)   Area =      247.79 ( 92.5 %)   Delay =   439.44 ps  ( 44.8 %)               
ABC: Path  0 --      14 : 0    1 pi      A =   0.00  Df =   7.9   -4.9 ps  S =  17.4 ps  Cin =  0.0 ff  Cout =   4.0 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --      39 : 1    3 BUFX4   A =   2.82  Df =  56.0  -20.4 ps  S =  22.5 ps  Cin =  3.9 ff  Cout =  16.3 ff  Cmax = 999.3 ff  G =  395  
ABC: Path  2 --      43 : 2    2 XNOR2X1 A =   4.69  Df = 129.4  -30.9 ps  S =  76.3 ps  Cin =  5.1 ff  Cout =  10.0 ff  Cmax = 228.3 ff  G =  190  
ABC: Path  3 --      54 : 2    3 XNOR2X1 A =   4.69  Df = 217.1  -28.2 ps  S = 104.5 ps  Cin =  5.1 ff  Cout =  16.0 ff  Cmax = 228.3 ff  G =  302  
ABC: Path  4 --      55 : 2    5 XNOR2X1 A =   4.69  Df = 310.9  -31.9 ps  S =  90.0 ps  Cin =  5.1 ff  Cout =  13.1 ff  Cmax = 228.3 ff  G =  253  
ABC: Path  5 --      65 : 2    3 NOR2X1  A =   2.35  Df = 356.1  -27.5 ps  S =  44.9 ps  Cin =  2.3 ff  Cout =   6.2 ff  Cmax =   0.0 ff  G =  262  
ABC: Path  6 --      70 : 2    1 NAND2X1 A =   1.88  Df = 393.8  -32.4 ps  S =  49.8 ps  Cin =  2.0 ff  Cout =   5.6 ff  Cmax =   0.0 ff  G =  265  
ABC: Path  7 --      71 : 2    1 XNOR2X1 A =   4.69  Df = 439.4  -13.3 ps  S =  27.7 ps  Cin =  5.1 ff  Cout =   0.0 ff  Cmax = 228.3 ff  G =    0  
ABC: Start-point = pi13 (\hv_i [15]).  End-point = po2 (\data_o [2]).
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ABC: + write_blif <abc-temp-dir>/output.blif 

22.3.2. Re-integrating ABC results.
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ABC RESULTS:            AND2X1 cells:        4
ABC RESULTS:            AND2X2 cells:        2
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ABC RESULTS:           AOI21X1 cells:        1
ABC RESULTS:             BUFX2 cells:        6
ABC RESULTS:             BUFX4 cells:        1
ABC RESULTS:           NAND2X1 cells:       11
ABC RESULTS:            NOR2X1 cells:        2
ABC RESULTS:           XNOR2X1 cells:       32
ABC RESULTS:            XOR2X1 cells:        8
ABC RESULTS:        internal signals:       63
ABC RESULTS:           input signals:       16
ABC RESULTS:          output signals:       12
Removing temp directory.

22.4. Extracting gate netlist of module `\hamming16t11d_enc' to `<abc-temp-dir>/input.blif'..
Extracted 32 gates and 43 wires to a netlist network with 11 inputs and 5 outputs.

22.4.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Library "gscl45nm" from "/home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib" has 25 cells (6 skipped: 4 seq; 2 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.36 MB. Time =     0.00 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
ABC: + read_constr -v /home/gcabo/BSC/bsc_pmu/synth/FT-resource-comp/synth.constr 
ABC: Setting driving cell to be "INVX1".
ABC: Setting output load to be 0.015000.
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime -D 10 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 10 
ABC: + &put 
ABC: + buffer 
ABC: + upsize -D 10 
ABC: + dnsize -D 10 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =     22 (  4.5 %)   Cap =  6.7 ff (  0.9 %)   Area =      101.37 ( 95.5 %)   Delay =   354.83 ps  ( 27.3 %)               
ABC: Path  0 --       7 : 0    1 pi      A =   0.00  Df =   7.9   -4.9 ps  S =  17.4 ps  Cin =  0.0 ff  Cout =   4.0 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --      20 : 1    3 BUFX4   A =   2.82  Df =  56.0  -20.5 ps  S =  22.3 ps  Cin =  3.9 ff  Cout =  16.1 ff  Cmax = 999.3 ff  G =  392  
ABC: Path  2 --      27 : 2    1 XOR2X1  A =   4.69  Df = 115.3  -24.8 ps  S =  59.2 ps  Cin =  5.3 ff  Cout =   5.6 ff  Cmax = 223.3 ff  G =  100  
ABC: Path  3 --      28 : 2    1 XNOR2X1 A =   4.69  Df = 180.0  -22.3 ps  S =  54.5 ps  Cin =  5.1 ff  Cout =   5.6 ff  Cmax = 228.3 ff  G =  104  
ABC: Path  4 --      29 : 2    2 XNOR2X1 A =   4.69  Df = 244.3  -22.4 ps  S =  54.6 ps  Cin =  5.1 ff  Cout =   5.6 ff  Cmax = 228.3 ff  G =  105  
ABC: Path  5 --      37 : 2    1 XNOR2X1 A =   4.69  Df = 308.8  -22.5 ps  S =  54.9 ps  Cin =  5.1 ff  Cout =   5.7 ff  Cmax = 228.3 ff  G =  106  
ABC: Path  6 --      38 : 2    1 XOR2X1  A =   4.69  Df = 354.8  -13.3 ps  S =  32.0 ps  Cin =  5.3 ff  Cout =   0.0 ff  Cmax = 223.3 ff  G =    0  
ABC: Start-point = pi6 (\data_i [0]).  End-point = po4 (\ocheck_int).
ABC: + write_blif <abc-temp-dir>/output.blif 

22.4.2. Re-integrating ABC results.
ABC RESULTS:             BUFX4 cells:        1
ABC RESULTS:           XNOR2X1 cells:       14
ABC RESULTS:            XOR2X1 cells:        7
ABC RESULTS:        internal signals:       27
ABC RESULTS:           input signals:       11
ABC RESULTS:          output signals:        5
Removing temp directory.
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22.5. Extracting gate netlist of module `\instances' to `<abc-temp-dir>/input.blif'..
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Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

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22.6. Extracting gate netlist of module `\reg_sbf(IN_WIDTH=16)' to `<abc-temp-dir>/input.blif'..
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Extracted 32 gates and 67 wires to a netlist network with 34 inputs and 2 outputs.

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22.6.1. Executing ABC.
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Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Library "gscl45nm" from "/home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib" has 25 cells (6 skipped: 4 seq; 2 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.36 MB. Time =     0.00 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
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ABC: + read_constr -v /home/gcabo/BSC/bsc_pmu/synth/FT-resource-comp/synth.constr 
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ABC: Setting driving cell to be "INVX1".
ABC: Setting output load to be 0.015000.
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime -D 10 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 10 
ABC: + &put 
ABC: + buffer 
ABC: + upsize -D 10 
ABC: + dnsize -D 10 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =     32 (  0.0 %)   Cap =  4.9 ff (  0.0 %)   Area =      146.42 (100.0 %)   Delay =   278.95 ps  ( 31.2 %)               
ABC: Path  0 --      18 : 0    1 pi      A =   0.00  Df =  10.3   -2.0 ps  S =  20.8 ps  Cin =  0.0 ff  Cout =   5.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --      59 : 2    1 XNOR2X1 A =   4.69  Df =  71.0  -23.5 ps  S =  55.1 ps  Cin =  5.1 ff  Cout =   5.6 ff  Cmax = 228.3 ff  G =  104  
ABC: Path  2 --      60 : 2    1 XNOR2X1 A =   4.69  Df = 133.4  -21.2 ps  S =  51.7 ps  Cin =  5.1 ff  Cout =   5.0 ff  Cmax = 228.3 ff  G =   95  
ABC: Path  3 --      62 : 2    1 XNOR2X1 A =   4.69  Df = 184.1  -12.2 ps  S =  54.5 ps  Cin =  5.1 ff  Cout =   5.6 ff  Cmax = 228.3 ff  G =  104  
ABC: Path  4 --      63 : 2    1 XNOR2X1 A =   4.69  Df = 246.5  -21.2 ps  S =  51.7 ps  Cin =  5.1 ff  Cout =   5.0 ff  Cmax = 228.3 ff  G =   95  
ABC: Path  5 --      68 : 2    1 XNOR2X1 A =   4.69  Df = 279.0   -2.8 ps  S =  27.7 ps  Cin =  5.1 ff  Cout =   0.0 ff  Cmax = 228.3 ff  G =    0  
ABC: Start-point = pi17 (\rego_i [3]).  End-point = po1 (\error_o).
ABC: + write_blif <abc-temp-dir>/output.blif 

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22.6.2. Re-integrating ABC results.
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